HDMP-0452

Features: • Supports 1.0625 GBd fibre channel operation• Supports 1.25 GBd Gigabit Ethernet (GE) operation• Quad PBC/CDR in one package• CDR location determined by choice of cable input/output• Valid amplitude detection on FM_NODE[0] input• Equalizers on all inp...

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SeekIC No. : 004361032 Detail

HDMP-0452: Features: • Supports 1.0625 GBd fibre channel operation• Supports 1.25 GBd Gigabit Ethernet (GE) operation• Quad PBC/CDR in one package• CDR location determined by choice of ...

floor Price/Ceiling Price

Part Number:
HDMP-0452
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/6

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Product Details

Description



Features:

• Supports 1.0625 GBd fibre channel operation
• Supports 1.25 GBd Gigabit Ethernet (GE) operation
• Quad PBC/CDR in one package
• CDR location determined by choice of cable input/output
• Valid amplitude detection on FM_NODE[0] input
• Equalizers on all inputs
• High speed LVPECL I/O
• Buffered Line Logic (BLL) outputs (no external bias resistors required)
• 0.66 W typical power at VCC = 3.3 V
• 44 pin, 10 mm, low cost plastic QFP package



Application

• RAID, JBOD, BTS cabinets
• 1 => 1-4 serial buffer with or w/o CDR



Pinout

  Connection Diagram


Specifications

SYMBOL Parameter Units MIN MAX
VCC Supply Voltage V -0.7 4.0
VIN,LVTTL LVTTL Input Voltage V -0.7 4.0
VIN,HS_IN HS_IN Input Voltage (Differential) mA 1.3 VCC
IO,LVTTL LVTTL Output Sink/Source Current mA ±13
Tstg Storage Temperature °C -65 +150
TJ Junction temperature °C 0 +125



Description

The HDMP-0452 is a Quad Port Bypass Circuit (PBC) with a Clock and Data Recovery (CDR) circuit included. This device minimizes part count, cost and jitter accumulation while repeating incoming signals. Port Bypass Circuits are used in hard disk arrays constructed in Fibre Channel Arbitrated Loop (FC-AL) configurations. By using Port Bypass Circuits, hard disks may be pulled out or swapped while other disks in the array are available to the system.

A Port Bypass Circuit (PBC) consists of multiple 2:1 multiplexers daisy chained along with a CDR. Each port has two modes of operation: "disk in loop" and "disk bypassed". When the "disk in loop" mode is selected, the loop goes into and out of the disk drive at that port. For example, data goes from the HDMP-0452's TO_NODE[n]± differential output pins to the Disk Drive Transceiver IC's (e.g., an HDMP-1536A) Rx± differential input pins. Data from the Disk Drive Transceiver IC's Tx± differential outputs goes to the HDMP-0452's FM_NODE[n]± differential input pins. Figures 3 and 4 show connection diagrams for disk drive array applications. When the "disk bypassed" mode is selected, the disk drive is either absent or nonfunctional and the loop bypasses the hard disk.

The "disk bypassed" mode of HDMP-0452  is enabled by pulling the BYPASS[n] pin low. Leave BYPASS[n] floating to enable the "disk in loop" mode. HDMP- 0452s may be cascaded with other members of the HDMP-04XX/ HDMP-05XX family through the FM_LOOP and TO_LOOP pins to accommodate any number of hard disks. See Table 2 to identify which of the 5 cells (0:4) will provide FM_LOOP and TO_LOOP pins (cable connections). The unused cells in this PBC may be bypassed by using pulldown resistors on the BYPASS[n] pins for these cells.

 




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