HD44102CH

The HD44102CH is a column (segment) driver for dot matrix liquid crystal graphic display systems,storing the display data transferred from a 4-bit or 8-bit microcomputer in the internal display RAM and generating dot matrix liquid crystal driving signals.Each bit data of display RAM corresponds to on/off state of each dot of a liquid crystal display to provide more nexiote man character display.

The HD44102CH has the following features including:(1)dot matrix liquid crystal graphic display column driver incorporating display RAM; (2)interfaces with 4-bit or 8-bit MPU; (3)RAM data directly displayed by internal display RAM; (4)display RAM capacity: 50 x 8 x 4 (1600 bits); (5)internal liquid crystal display driver circuit(segment output): 50 segment signal drivers; (6)duty factor (can be controlled by ezternal input waveform).The HD44102CH is produced by the CMOS process.Therefore, the combination of HD44102CH with a CMOS microcontrollercan complete portable battery-driven unit utilizing the liquid crystal display's low power dissipation.The combination of HD44102CH with the row (common) driver HD44103CH facilitates dot matrix liquid crystal graphic display system configuration.

The absolute maximum ratings of the HD44102CH are:(1)supply voltage:-0.3 to 7.0V; (2)input voltage:-0.3 to Vcc+0.3V; (3)operating temperature:-25 to 75; (4)storage temperature:-55 to 125.Execute instructions other than status read in 4-bit length each. The busy flag is set at the fall of the second E signal. The status read is executed once. Afterthe execution of the status read, the first 4 bits are considered the hh order 4 bits. Therefore, if the busy flag is checked after the transfer of the high order 4 bits, retransfer data from the higher order bits.No busy check is required in the transfer between the high and low order bits.The Z address counter is a 5-bit counter that counts up at the fall of CL signal and generates an address for outputting the display data synchronized with the signal.0 is preset to the low order 3 bits and a display start page to the high order 2 bits by the FRM signal.