HCT670

The 74HC/HCT670 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). 74HC/HCT670  are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT670 are 16-bit 3-state register files organized as 4 words of 4 bits each. Separated read and write address inputs (RA, RB and WA, WB) and enable inputs (RE and WE) are available, permitting simultaneous writing into one word location and reading from another location. The 4-bit word to be stored is presented to four data inputs (D0 to D3). The WA and WB inputs determine the location of the stored word. When the WE input is LOW, the data is entered into the addressed location. The addressed location remains transparent to the data while the WE input is LOW. Data supplied at the inputs will be read out in true (non-inverting) form from the 3-state outputs (Q0 to Q3). Dn and Wn inputs are inhibited when WE is HIGH.

Direct acquisition of data stored in any of the four registers is made possible by individual read address inputs (RA and RB). The addressed word appears at the four outputs when the RE is LOW. Data outputs are in the high impedance OFF-state when RE is HIGH. This permits outputs to be tied together to increase the word capacity to very large numbers. Design of the read enable signals for the stacked 74HC/HCT670  devices must ensure that there is no overlap in the LOW levels which would cause more than one output to be active at the same time. Parallel expansion to generate n-bit words is accomplished by driving the enable and address inputs of each device in parallel.