HCT652

The 74HC/HCT652 are high-speed SI-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with Jedec standard no. 7A.

The 74HC/HCT652 consist of 8 non-inverting bus transceiver circuits with 3-state outputs, D-type flip-flops and central circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Data on the "A" or "B" or both buses, will be stored in the internal registers, at theappropriate clock pins (CPAB or CPBA) regardless of the select pins (SAB and SBA) or output enable (OEAB and OEBA) control pins. Depending on the select inputs SAB and SBA data can directly go from input to output (real time mode) or data can be controlled by the clock (storage mode), this is when the output enable pins this operating mode permits. The output enable pins OEAB and OEBA determine the operation mode of the transceiver. When OEAB is LOW, no data transmission from An to Bn is possible and when OEBA is HIGH, there is no data transmission from Bn to An possible. When SAB and SBA are in the real time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration each output reinforces its input. Thus when all other data sources to the two sets of bus lines are at high-impedance, each set of the bus lines will remain at its last state. This 74HC/HCT652  type differs from the HC/HCT646 in one extra bus-management function. This is the possibility to transfer stored "A data to the "B" bus and transfer stored "B" data to the "A" bus at the same time.

The examples at the application information demonstrate all bus management functions. Schmitt-trigger action in the clock inputs makes the 74HC/HCT652  circuit highly tolerant to slower clock rise and fall times.