HCS573MS

Features:

• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm2/mg
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day (Typ)
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s
• Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse
• Latch-Up Free Under Any Conditions
• Fanout (Over Temperature Range)
- Bus Driver Outputs - 15 LSTTL Loads
• Military Temperature Range: -55oC to +125oC
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
- VIL = 0.3 VCC Max
- VIH = 0.7 VCC Min
• Input Current Levels Ii 5A at VOL, VOH




Pinout






Specifications

Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . . -.0.5V to +7.0V
Input Voltage Range, All Inputs . . . . . . . . . . . . ...-0.5V to VCC +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . ...±10mA
DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . .. .±25mA
(All Voltage Reference to the VSS Terminal)
Storage Temperature Range (TSTG) . . . . . . . . . . ......-65 to +150
Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . ..+265
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . ...+175
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... Class 1

CAUTION: As with all semiconductors, stress listed under "Absolute Maximum Ratings" may be applied to devices (one at a time) without resulting in permanent damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed under "Electrical Performance Characteristics" are the only conditions recommended for satisfactory device operation..




Description

The Intersil HCS573MS is a Radiation Hardened octal transparent three-state latch with an active low output enable. The HCS573MS utilizes advanced CMOS/SOS technology. The outputs are transparent to the inputs when the Latch Enable (LE) is HIGH. When the Latch Enable (LE) goes LOW, the data is latched. The Output Enable (OE) controls the tri-state outputs. When the Output Enable (OE) is HIGH, the outputs are in the high impedance state. The latch operation is independent of the state of the Output Enable.

The HCS573MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family.

The HCS573MS is supplied in a 20 lead Ceramic flatpack (K suffix) or a SBDIP Package (D suffix).