Features: `SERIAL DATA INPUT - ACTIVE PARALLEL OUTPUT` STORAGE REGISTER CAPABILITY - MASTER CLEAR` CAN FUNCTION AS DEMULTIPLEXER` QUIESCENT CURRENT SPECIFIED UP TO 20V` STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS` INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25` 100% TESTED FOR QUI...
HCF4724B: Features: `SERIAL DATA INPUT - ACTIVE PARALLEL OUTPUT` STORAGE REGISTER CAPABILITY - MASTER CLEAR` CAN FUNCTION AS DEMULTIPLEXER` QUIESCENT CURRENT SPECIFIED UP TO 20V` STANDARDIZED SYMMETRICAL OUTP...
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Symbol |
Parameter |
Value |
Unit |
VDD |
Supply Voltage |
-0.5 to +22 |
V |
VI |
DC Input Voltage |
-0.5 to VDD + 0.5 |
V |
II |
DC Input Current |
± 10 |
mA |
PD |
Power Dissipation per Package |
200 |
mW |
Power Dissipation per Output Transistor |
100 |
mW | |
Top |
Operating Temperature |
-55 to +125 |
|
Tstg |
Storage Temperature |
-65 to +150 |
HCF4724B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages.
HCF4724B, an 8-bit addressable latch, is a serial-input, parallel output storage register that can perform a variety of functions. Data is input to a particular bit in the latch when the bit is addressed (by means of input A0, A1, A2) and when WRITE DISABLE is at a low level. When WRITE DISABLE is high, data entry is inhibited; however, all 8 outputs can be continuously read independent of WRITE DISABLE and address inputs. A master RESET input is available, which resets all bits to a logic "0" level when RESET and WRITE DISABLE are at a high level. When RESET is at a high level, and WRITE DISABLE is at a low level, the latch acts as a 1-of-8 demultiplexer; the bit that is addressed has an active output which follows the data input, while all unaddressed bits are held to a logic "0" level.