Features: ` MEDIUM SPEEDOPERATION fCL =8MHz TYP. AT 10V ` SYNCHRONOUS INTERNAL CARRY PROPA GATION ` RESET AND PRESET CAPABILITY `QUIESCENT CURRENT SPECIFIED TO 20V FOR HCC DEVICE ` 5V, 10V, AND 15V PARAMETRIC RATINGS`INPUT CURRENTOF 100nA AT 18V AND 25°C FOR HCC DEVICE ` 100% TESTEDFOR QUIESCENT C...
HCF4516B: Features: ` MEDIUM SPEEDOPERATION fCL =8MHz TYP. AT 10V ` SYNCHRONOUS INTERNAL CARRY PROPA GATION ` RESET AND PRESET CAPABILITY `QUIESCENT CURRENT SPECIFIED TO 20V FOR HCC DEVICE ` 5V, 10V, AND 15V ...
SeekIC Buyer Protection PLUS - newly updated for 2013!
268 Transactions
All payment methods are secure and covered by SeekIC Buyer Protection PLUS.
Symbol | Parameter |
Value |
Unit |
VDD | Supply Voltage :HCC Types HCF Types |
0.5 to + 20 0.5 to + 18 |
V V |
VI | Input Voltage |
0.5 to VDD + 0.5 |
V |
II | DC Input Current (any one input) |
± 10 |
mA |
Ptot | Total Power Dissipation (per package) Dissipation per Output Transistor for Top = Full Package-temperature Range |
200 100 |
mW mW |
Top | Operating Temperature : HCC Types HCF Types |
55 to + 125 40 to + 85 |
|
Tstg | Storage Temperature |
65 to + 150 |
In the HCC/HCF4510B and HCC/HCF4516B series, the HCC4510B, HCC4516B (extended temperature range) and the HCF4510B, HCF4516B (intermediate temperature range) are monolithic integrated circuits available in 16-lead dual in-line plastic or ceramic package and plastic micro package. The HCC/HCF4510B Presettable BCD Up/Down Counter and the HCC/HCF4516B Presettable Binary Up/Down Counter consist of four synchronously clocked D-type flip-flops (with a gating structure to provide T-type flip-flop capability) connected as counters. These counters can be cleared by a high level on the RESET line,and can be preset to any binary number present on the jaminputs by ahigh level on thePRESET ENABLE line. The HCC/HCF4510B and HCC/HCF4516B will count out of non-BCD counter states in a maximum of two clock pulses in the up mode, and a maximum of four clock pulses in the down mode. If the CARRY-IN input is held low, the counter advances up or down on each positive-going clock transition. Synchronous cascading is accomplished by connecting all clock inputs in parallel and connecting the CARRY-OUT of a less significant stage to the CARRY- IN of a more significant stage. The HCC/HCF4510B and HCC/HCF4516B can be cascaded in the ripple mode by connecting the CARRY- OUT to the clock of the next stage. If the UP/DOWN input changes during a terminal count, the CARRY-OUT must be gated with the clock, and the UP/DOWN input must change while the clock is high. Thismethod provides a clean clock signal tothe subsequent counting stage.