HCF4085B

Features: ` MEDIUM-SPEED OPERATION tPHL = 90ns, tPLH = 125ns (Typ.) at 10V` INDIVIDUAL INHIBIT CONTROLS` QUIESCENT CURRENT SPECIFIED UP TO 20V` STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS`5V, 10V AND 15V PARAMETRIC RATINGS` INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25` 100% TEST...

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HCF4085B Picture
SeekIC No. : 004359689 Detail

HCF4085B: Features: ` MEDIUM-SPEED OPERATION tPHL = 90ns, tPLH = 125ns (Typ.) at 10V` INDIVIDUAL INHIBIT CONTROLS` QUIESCENT CURRENT SPECIFIED UP TO 20V` STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS`5V, 10...

floor Price/Ceiling Price

Part Number:
HCF4085B
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/24

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Product Details

Description



Features:

` MEDIUM-SPEED OPERATION tPHL = 90ns, tPLH = 125ns (Typ.) at 10V
` INDIVIDUAL INHIBIT CONTROLS
` QUIESCENT CURRENT SPECIFIED UP TO 20V
` STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS
`5V, 10V AND 15V PARAMETRIC RATINGS
` INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25
` 100% TESTED FOR QUIESCENT CURRENT
` MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES
   CMOS DEVICES"



Pinout

  Connection Diagram


Specifications

Symbol
Parameter
Value
Unit
VDD
Supply Voltage
-0.5 to +22
V
VI
DC Input Voltage
-0.5 to VDD + 0.5
V
II
DC Input Current
± 10
mA
PD
Power Dissipation per Package
200
mW
Power Dissipation per Output Transistor
100
mW
Top
Operating Temperature
-55 to +125
Tstg
Storage Temperature
-65 to +150
Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied.

All voltage values are referred to VSS pin voltage.


Description

HCF4085B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages.

HCF4085B contains a pair of AND-OR INVERT gates, each consisting of two 2-input AND gates driving a 3-input NOR gate. Individual inhibit controls are provided for both A-O-I gates.




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