HCF4076B

Features: ` THREE STATE OUTPUTS` INPUT DISABLE WITHOUT GATING THE CLOCK` GATED OUTPUT CONTROL LINES FOR ENABLING OR DISABLING THE OUTPUTS` BUFFERED INPUTS AND OUTPUTS` QUIESCENT CURRENT SPECIFIED UP TO 20V` 5V, 10V AND 15V PARAMETRIC RATINGS` INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA ...

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HCF4076B Picture
SeekIC No. : 004359684 Detail

HCF4076B: Features: ` THREE STATE OUTPUTS` INPUT DISABLE WITHOUT GATING THE CLOCK` GATED OUTPUT CONTROL LINES FOR ENABLING OR DISABLING THE OUTPUTS` BUFFERED INPUTS AND OUTPUTS` QUIESCENT CURRENT SPECIFIED UP...

floor Price/Ceiling Price

Part Number:
HCF4076B
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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268 Transactions

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Upload time: 2024/11/21

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Product Details

Description



Features:

` THREE STATE OUTPUTS
` INPUT DISABLE WITHOUT GATING THE CLOCK
` GATED OUTPUT CONTROL LINES FOR ENABLING OR DISABLING THE OUTPUTS
` BUFFERED INPUTS AND OUTPUTS
` QUIESCENT CURRENT SPECIFIED UP TO 20V
` 5V, 10V AND 15V PARAMETRIC RATINGS
` INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25
` 100% TESTED FOR QUIESCENT CURRENT
` MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES
    CMOS DEVICES"



Pinout

  Connection Diagram


Specifications

Symbol
Parameter
Value
Unit
VDD
Supply Voltage
-0.5 to +22
V
VI
DC Input Voltage
-0.5 to VDD + 0.5
V
II
DC Input Current
± 10
mA
PD
Power Dissipation per Package
200
mW
Power Dissipation per Output Transistor
100
mW
Top
Operating Temperature
-55 to +125
Tstg
Storage Temperature
-65 to +150
Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied.

All voltage values are referred to VSS pin voltage.


Description

HCF4076B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. HCF4076B is a four bit register consisting of D-TYPE flip-flops that feature three state outputs. Data Disable inputs are provided to control the entry of data into the flip-flops. When both Data Disable inputs are low, data at the D inputs are loaded into their respective flip-flops on the next positive transition of the clock input. Output Disable inputs are also provided. When the Output Disable inputs are both low, the normal logic states of the four outputs are available to the load. The outputs are disabled independently of the clock by a high logic level at either Output Disable input, and present a high impedance.




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