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HCF4043B

Features: `QUIESCENT CURRENT SPECIFIED UP TO 20V` 3-LEVEL OUTPUTS WITH COMMON OUTPUT ENABLE` SEPARATE SET AND RESET INPUT FOR EACH LATCH` 5V, 10V AND 15V PARAMETRIC RATINGS` INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25` 100% TESTED FOR QUIESCENT CURRENT` MEETS ALL REQUIREMENTS OF JE...

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SeekIC No. : 004359659 Detail

HCF4043B: Features: `QUIESCENT CURRENT SPECIFIED UP TO 20V` 3-LEVEL OUTPUTS WITH COMMON OUTPUT ENABLE` SEPARATE SET AND RESET INPUT FOR EACH LATCH` 5V, 10V AND 15V PARAMETRIC RATINGS` INPUT LEAKAGE CURRENT II...

HCF4043B Data Sheet

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Part Number:
HCF4043B
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/21

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Product Details

Description



Features:

`QUIESCENT CURRENT SPECIFIED UP TO 20V
` 3-LEVEL OUTPUTS WITH COMMON OUTPUT ENABLE
` SEPARATE SET AND RESET INPUT FOR EACH LATCH
` 5V, 10V AND 15V PARAMETRIC RATINGS
` INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25
` 100% TESTED FOR QUIESCENT CURRENT
` MEETS ALL REQUIREMENTS OF JEDEC JESD13B " STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES
    CMOS DEVICES"


Pinout

Connection Diagram


Specifications

Symbol
 Parameter
Value
Unit
VDD
 Supply Voltage
-0.5 to +22
V
VI
 DC Input Voltage
-0.5 to VDD + 0.5
V
II
 DC Input Current
± 10
mA
PD
 Power Dissipation per Package
200
mW
Power Dissipation per Output Transistor
100
mW
Top
 Operating Temperature
-55 to +125
Tstg
 Storage Temperature
-65 to +150
Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied.

All voltage values are referred to VSS pin voltage.


Description

The HCF4043B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. The HCF4043B is a quad cross-coupled 3-state CMOS NOR latch. Each latch has a separate Q output and individual SET and RESET input. The Q outputs are controlled by a common ENABLE input. A logic "1" or "high" on the ENABLE inputs connects the latch states to the Q outputs. A logic "0" or "low" on the ENABLE input disconnects the latch states from the Q outputs, resulting in an open circuit condition on the Q outputs. The open circuit feature allows common bussing of the outputs.




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