Features: · INVERT INPUTS ON ALL ADDERS FOR SUM COMPLEMENTING APPLICATIONS· FULLY STATIC OPERATION...DC TO 10MHz (Typ.) at VDD = 10V· BUFFERED INPUTS AND OUTPUTS· SINGLE PHASE CLOCKING· QUIESCENT CURRENT SPECIFIED UP TO 20V· STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS· INPUT LEAKAGE CURRENT II...
HCF4032B: Features: · INVERT INPUTS ON ALL ADDERS FOR SUM COMPLEMENTING APPLICATIONS· FULLY STATIC OPERATION...DC TO 10MHz (Typ.) at VDD = 10V· BUFFERED INPUTS AND OUTPUTS· SINGLE PHASE CLOCKING· QUIESCENT CU...
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· INVERT INPUTS ON ALL ADDERS FOR SUM COMPLEMENTING APPLICATIONS
· FULLY STATIC OPERATION...DC TO 10MHz (Typ.) at VDD = 10V
· BUFFERED INPUTS AND OUTPUTS
· SINGLE PHASE CLOCKING
· QUIESCENT CURRENT SPECIFIED UP TO 20V
· STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS
· INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25°C
· 100% TESTED FOR QUIESCENT CURRENT
· MEETS ALL REQUIREMENTS OF JEDEC JESD13B " STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES"
Symbol | Parameter² | Value | Unit |
VDD | Supply Voltage | -0.5 to +22 | V |
VI | DC Input Voltage | -0.5 to VDD + 0.5 | V |
II | DC Input Current | ± 10 | mA |
PD | Power Dissipation per Package | 200 | mW |
Power Dissipation per Output Transistor | 100 | mW | |
Top | Operating Temperature | -55 to +125 | |
Tstg | Storage Temperature | -65 to +150 |
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied.
All voltage values are referred to VSS pin voltage.
The HCF4032B is a monolithic integrated circuitfabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. The HCF4032B consists of three serial adder circuits with common CLOCK and CARRY-RESET inputs. Each adder has two provisions for two serial DATA INPUT signals and an INVERT command signal. When the command signal is a logical "1", the sum is complemented.
Data words enter the adder with the least significant bit first; the sign bit trails. The output of HCF4032B is the MOD 2 sum of the input bits plus the carry from the previous bit position. The carry is only added at the positive going clock transition, thus,for spike-free operation the input data transitions should occur as soon as possible after the triggering edge. The CARRY is reset to a logical "0" at the end of each word by applying a logical "1" signal to a CARRY-RESET input one bit position before the application of the first bit of the next word.