HCF4031B

Features:

`FULLY STATIC OPERATION : DC to 16MHz (TYP.) @ VDD VSS = 15V
`STANDARD TTL DRIVE CAPABILITY ON Q OUTPUT
`RECIRCULATION CAPABILITY
`THREE CASCADING MODES : DIRECT CLOCKING FOR HIGH-SPEED OPERATION DELAYEDCLOCKINGFORREDUCEDCLOCK DRIVE REQUIREMENTS ADDITIONAL 1/2 STAGE FOR SLOW CLOCKS
`QUIESCENT CURRENT SPECIFIED TO 20V FOR HCC DEVICE
`STANDARDIZED, SYMMETRICAL OUTPUT CHARACTERISTICS
`5V, 10V, AND 15V PARAMETRIC RATINGS
`INPUT CURRENT OF 100nA at 18V AND 25 FOR HCC DEVICE
`100% TESTEDFOR QUIESCENT CURRENT
`MEETSALLREQUIREMENTSOFJEDECTENTATIVE STANDARD NO. 13A, "STANDARD SPECIFICATIONS FOR DESCRIPTION OF "B" SERIESCMOS DEVICES"


Pinout




Specifications

Symbol	Parameter	Value	Unit
VDD*	Supply Voltage :HCC Types HCF Types	0.5 to + 20 0.5 to + 18	V V
Vi	Input Voltage	0.5 to VDD + 0.5	V
II	DC Input Current (any one input)	± 10	mA
Ptot	Total Power Dissipation (per package) Dissipation per Output Transistor for Top = Full Package-temperature Range	200 100	mW mW
Top	Operating Temperature : HCC Types HCF Types	55 to + 125 40 to + 85
Tstg	Storage Temperature	65 to + 150

Description

In the HCC/HCF4031B  series, the HCC4031B (extended temperature range) and HCF4031B (intermediate temperature range) are monolithic integrated circuits, available in 16-lead dual in-line plastic or ceramic package.

The HCC/HCF4031B is a static shift register that contains 64 D-type, master-slave flip-flop stages and one stage which is a D-typemaster flip-flop only (referred to as a 1/2 stage). The logic level present at the DATA input is transferred into the first stage and shifted one stage at each positive-going clock transition. Maximum clock frequencies up to 16 Megahertz (typical) can be obtained. Because fully static operation is allowed, information can be permanently stored with the clock line in either the low or high state. The HCC/HCF4031B has a MODE CONTROL input that, when in the high state, allows operation in the recirculating mode. The MODE CONTROLinput can also beused to select between two separate data sources. Register packages can be cascaded and the clock lines driven directly for high-speed operation. Alternatively, a delayed clock output(CLD) isprovided that enables cascading reg- ister packages while allowing reduced clock drive fan-out and transition-time requirements. A third cascading option makes use of the Q' output from the 1/2 stage, which is available on the next negative-going transition of the clock after the Q output occurs. This delayed output, like the delayed clock CLD, is used with clocks having slow rise and fall times.