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HCF4025B

Features: ·PROPAGATION DELAY TIME : tPD = 50ns (TYP.) at VDD = 10V CL = 50pF·BUFFERED INPUTS AND OUTPUTS·STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS·QUIESCENT CURRENT SPECIFIED UP TO 20V·5V, 10V AND 15V PARAMETRIC RATINGS·INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25°C·100% TESTE...

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SeekIC No. : 004359644 Detail

HCF4025B: Features: ·PROPAGATION DELAY TIME : tPD = 50ns (TYP.) at VDD = 10V CL = 50pF·BUFFERED INPUTS AND OUTPUTS·STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS·QUIESCENT CURRENT SPECIFIED UP TO 20V·5V, 10V...

HCF4025B Data Sheet

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Part Number:
HCF4025B
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

·PROPAGATION DELAY TIME : tPD = 50ns (TYP.) at VDD = 10V CL = 50pF
·BUFFERED INPUTS AND OUTPUTS
·STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS
·QUIESCENT CURRENT SPECIFIED UP TO 20V
·5V, 10V AND 15V PARAMETRIC RATINGS
·INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25°C
·100% TESTED FOR QUIESCENT CURRENT
·MEETS ALL REQUIREMENTS OF JEDEC JESD13B " STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES"


Pinout

Connection Diagram


Specifications

Symbol
Rating
Value
Unit
VDD
 Supply Voltage
0.5 to + 22
V
Vi
 DC Input Voltage
0.5 to VDD + 0.5
V
II
 DC Input Current
± 10
mA
PD

Power Dissipation per package

Power Dissipation per Output Transistor
200

100
mW

mW
Top
 Operating Temperature
-55 to +125
°C
Tstg
 Storage Temperature
65 to + 150
°C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to VSS pin voltage.


Description

The HCF4025B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. The HCF4025B TRIPLE 3-INPUT NOR GATE provides the system designer with direct implementation of the NOR function and supplement the existing family of CMOS gates. All inputs and outputs are buffered.




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