HCF40194B

Features: · MEDIUM SPEED OPERATION :12 MHz (Typ.) at 10V· FULLY STATIC OPERATION· SYNCHRONOUS PARALLEL OR SERIAL OPERATION· ASYNCHRONOUS MASTER RESET· STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS· QUIESCENT CURRENT SPECIF. UP TO 20V· 5V, 10V AND 15V PARAMETRIC RATINGS· INPUT LEAKAGE CURRENT II=...

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HCF40194B Picture
SeekIC No. : 004359638 Detail

HCF40194B: Features: · MEDIUM SPEED OPERATION :12 MHz (Typ.) at 10V· FULLY STATIC OPERATION· SYNCHRONOUS PARALLEL OR SERIAL OPERATION· ASYNCHRONOUS MASTER RESET· STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS...

floor Price/Ceiling Price

Part Number:
HCF40194B
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/24

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Product Details

Description



Features:

· MEDIUM SPEED OPERATION :12 MHz (Typ.)  at  10V
· FULLY STATIC OPERATION
· SYNCHRONOUS PARALLEL OR SERIAL OPERATION
· ASYNCHRONOUS MASTER RESET
· STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS
·  QUIESCENT CURRENT SPECIF. UP TO 20V
· 5V, 10V AND 15V PARAMETRIC RATINGS
· INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25°C
· 100% TESTED FOR QUIESCENT CURRENT n MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD PECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES"




Pinout

  Connection Diagram


Specifications

Symbol Parameter² Value Unit
VDD Supply Voltage -0.5 to +22
V
VI DC Input Voltage -0.5 to VDD + 0.5 V
II DC Input Current ± 10 mA
PD Power Dissipation per Package 200 mW
Power Dissipation per Output Transistor 100 mW
Top Operating Temperature -55 to +125
Tstg Storage Temperature -65 to +150

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied.
All voltage values are referred to VSS pin voltage.




Description

HCF40194B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP packages. HCF40194B is a universal shift register featuring parallel inputs, parallel outputs, SHIFT RIGHT and SHIFT LEFT serial inputs, and a direct overriding clear input. In the parallel-load mode (S0 and S1 are high), data is loaded into the associated flip-flop and appears at the output after the positive transition of the CLOCK input. During loading, serial data flow is inhibited. Shift right and shift left are synchronously accomplished on the positive clock edge with data entered at the SHIFT RIGHT and SHIFT LEFT serial inputs,respectively. Clocking of the register  is inhibited when both mode control inputs are low. When low,the RESET input resets all stages and forces all outputs low. HCF40194B is similar to industry types 340194 and MC40194.     




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