HCF40192B

Specifications Symbol Parameter Value Unit VDD* Supply Voltage :HCC Types HCF Types 0.5 to + 20 0.5 to + 18 VV Vi Input Voltage 0.5 to VDD + 0.5 V II DC Input Current (any one input) ± 10 mA Ptot Total Power Dissipation (per package)Dissipation per Output T...

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SeekIC No. : 004359636 Detail

HCF40192B: Specifications Symbol Parameter Value Unit VDD* Supply Voltage :HCC Types HCF Types 0.5 to + 20 0.5 to + 18 VV Vi Input Voltage 0.5 to VDD + 0.5 V II DC Input Curren...

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Part Number:
HCF40192B
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/5/31

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Product Details

Description



Specifications

Symbol Parameter Value Unit
VDD* Supply Voltage :HCC Types
   HCF Types
0.5 to + 20
0.5 to + 18
V
V
Vi Input Voltage 0.5 to VDD + 0.5 V
II DC Input Current (any one input) ± 10 mA
Ptot Total Power Dissipation (per package)
Dissipation per Output Transistor
for Top = Full Package-temperature Range
200

100
mW

mW
Top Operating Temperature : HCC Types
   HCF Types
55 to + 125
40 to + 85
°C
°C
Tstg Storage Temperature 65 to + 150 °C



Description

In the HCC/HCF40192B, HCC/HCF40193B series, the HCC40192B, HCC40193B, (extended temperature range) and the HCF40192B, HCF40193B (intermediate temperature range) are monolithic integrated circuits, available in 16-lead dual in-line plastic or ceramic package and platic micro package. The HCC/HCF40192B, HCC/HCF40193B Presettable BCD Up/Down Counter Binary Up/Down Counter each consist of 4 synchronously clocked, gated "D" type flip-flops connected as a counter. The inputs consist of 4 individual jam lines, a PRESET ENABLE control, individual CLOCK UP and CLOCK DOWN signals and a master RESET. Four buffered Q signal outputs as well as CARRYand BORROW outputs for multiple-stage counting schemes are provided. The counter is cleared so that all outputs are in a low state by a high on the RESET line. A RESET is accomplished asynchronously with the clock. Each output is individually programmable asynchronouslywith theclock to the level on the corresponding jam input when thePRESET ENABLE control is low. The counter counts up one count on the positive clock edge of the CLOCK UP signal provided the CLOCK DOWN line is high. The counter counts down one count on the positive clock edge of the CLOCKDOWN signal provided the CLOCK UP line is high. The CARRY and BORROW signals are high when the counter is counting up or down. The CARRY signal goes low one-half clock cycle after the counter reaches its maximum count in the countup mode. The BORROW signal goes low one-half clock cycle after the counter reaches its minimum count in the count-down mode. Cascading of multiple packages is easily accomplished without the need for additional external circuitry by tying the BORROW and CARRY outputs to the CLOCK DOWN and CLOCK UP inputs, respectively, of the succeeding package.




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