HCF40160B

Features: · INTERNAL LOOK-AHEAD FOR FAST COUNTING· CARRY OUTPUT FOR CASCADING· SYNCHRONOUSLY PROGRAMMABLE· LOW-POWER TTL COMPATIBILITY· STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS· QUIESCENT CURRENT SPECIF. UP TO 20V· 5V, 10V AND 15V PARAMETRIC RATINGS· INPUT LEAKAGE CURRENT II= 100nA (MAX) AT...

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SeekIC No. : 004359625 Detail

HCF40160B: Features: · INTERNAL LOOK-AHEAD FOR FAST COUNTING· CARRY OUTPUT FOR CASCADING· SYNCHRONOUSLY PROGRAMMABLE· LOW-POWER TTL COMPATIBILITY· STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS· QUIESCENT CUR...

floor Price/Ceiling Price

Part Number:
HCF40160B
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/21

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Product Details

Description



Features:

· INTERNAL LOOK-AHEAD FOR FAST COUNTING
· CARRY OUTPUT FOR CASCADING
· SYNCHRONOUSLY PROGRAMMABLE
· LOW-POWER TTL COMPATIBILITY
· STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS
· QUIESCENT CURRENT SPECIF. UP TO 20V
· 5V, 10V AND 15V PARAMETRIC RATINGS
· INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25°C
· 100% TESTED FOR QUIESCENT CURRENT
· MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS  DEVICES"




Pinout

  Connection Diagram


Specifications

Symbol Parameter² Value Unit
VDD Supply Voltage -0.5 to +22
V
VI DC Input Voltage -0.5 to VDD + 0.5 V
II DC Input Current ± 10 mA
PD Power Dissipation per Package 200 mW
Power Dissipation per Output Transistor 100 mW
Top Operating Temperature -55 to +125
Tstg Storage Temperature -65 to +150

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied.
All voltage values are referred to VSS pin voltage.




Description

HCF40160B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. HCF40160B is 4-bit synchronous programmable counters. The CLEAR function is asynchronous. A low level at the CLEAR input sets all four outputs low regardless of the state of the CLOCK, LOAD and ENABLE inputs. A low level at the LOAD inputs disables the counter and causes the output to agree with the set-up data after the following CLOCK pulse regardless of the condition of the ENABLE inputs. Two count-enable inputs and a carry output (COUT) are instrumental in accomplishing this function. The carry look-ahead  circuitry provides for cascading counter for n-bit synchronous application without additional gating.Counting is enabled when both the PE and TE inputs are high. The TE input is fed forward to enable COUT. This enable output produces a positive output pulse with a duration approximately equal to the positive portion of the Q1 output. This positive overflow carry pulse can be used to enable successive cascaded stages.Logic transitions at the PE and TE inputs may occur when the clock is either high or low.




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