HCF4015B

Features: `MEDIUM SPEED OPERATION : 12MHz (typ.) CLOCK RATE AT VDD - VSS = 10V `FULLY STATIC OPERATION `8 MASTER-SLAVE FLIP-FLOPS PLUS INPUT AND OUTPUT BUFFERING `HIGH NOISE IMMUNITY .QUIESCENT CURRENT SPECIFIED TO 20V FOR HCC DEVICE `INPUT CURRENTOF 100nA AT 18V AND 25°C FOR HCC DEVICE `100% TEST...

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HCF4015B Picture
SeekIC No. : 004359624 Detail

HCF4015B: Features: `MEDIUM SPEED OPERATION : 12MHz (typ.) CLOCK RATE AT VDD - VSS = 10V `FULLY STATIC OPERATION `8 MASTER-SLAVE FLIP-FLOPS PLUS INPUT AND OUTPUT BUFFERING `HIGH NOISE IMMUNITY .QUIESCENT CURR...

floor Price/Ceiling Price

Part Number:
HCF4015B
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/21

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Product Details

Description



Features:

`MEDIUM SPEED OPERATION : 12MHz (typ.) CLOCK RATE AT VDD - VSS = 10V
`FULLY STATIC OPERATION
`8 MASTER-SLAVE FLIP-FLOPS PLUS INPUT AND OUTPUT BUFFERING
`HIGH NOISE IMMUNITY .QUIESCENT CURRENT SPECIFIED TO 20V FOR HCC DEVICE
`INPUT CURRENTOF 100nA AT 18V AND 25°C FOR HCC DEVICE
`100% TESTEDFOR QUIESCENT CURRENT
`5V, 10V, AND 15V PARAMETRIC RATINGS
`MEETSALLREQUIREMENTSOFJEDECTENTATIVE STANDARD NO. 13A, "STANDARD SPECIFICATIONS FOR DESCRIPTION OF "B" SERIESCMOS DEVICES"



Pinout

  Connection Diagram


Specifications

Symbol Parameter Value Unit
VDD* Supply Voltage :HCC Types
HCF Types
0.5 to + 20
0.5 to + 18
V
V
Vi Input Voltage 0.5 to VDD + 0.5 V
II DC Input Current (any one input) ± 10 mA
Ptot Total Power Dissipation (per package)
Dissipation per Output Transistor
for Top = Full Package-temperature Range
200
100
mW
mW
Top Operating Temperature : HCC Types
HCF Types
55 to + 125
40 to + 85

Tstg Storage Temperature 65 to + 150



Description

In the HCC/HCF4015B series,   the HCC4015B (extended temperature range) and HCF4015B (intermediate temperature range) are monolithic integrated circuits, available in 16-lead dual in-line plastic or ceramic package and plastic micropackage.

The HCC/HCF4015B consists of two identical, independent, 4-stageserial-input/parallel-output registers. Each register has independent CLOCK and RESET inputs as well as a single serial DATA input. "Q" outputsare available fromeach of the four stageson both registers. All register stages are D-type,master-slave flip-flops. The logic level present at the DATA input is transferred into the first register stage and shifted over one stage at each positive-going clock transition. Resetting of all stages is accomplished by ahigh level on the reset line. Register expansion to 8 stages using one HCC/HCF4015B package, or to more than 8 stagesusingadditional HCC/HCF4015B's ispossible.


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