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HCC4071B

Features: MEDIUM-SPEED OPERATION tPLH,tPHL = 60ns. (typ.) AT VDD = 10VQUIESCENT CURRENT SPECIFIED TO 20V FOR HCC DEVICE5V, 10V AND 15V PARAMETRIC RATINGSINPUT CURRENT OF 100nA AT 18V AND 25°C FOR HCC DEVICE100% TESTEDFOR QUIESCENT CURRENTMEETSALLREQUIREMENTSOF JEDECTEN- TATIVE STANDARD No13A, STA...

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HCC4071B: Features: MEDIUM-SPEED OPERATION tPLH,tPHL = 60ns. (typ.) AT VDD = 10VQUIESCENT CURRENT SPECIFIED TO 20V FOR HCC DEVICE5V, 10V AND 15V PARAMETRIC RATINGSINPUT CURRENT OF 100nA AT 18V AND 25°C FOR HC...

HCC4071B Data Sheet

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Part Number:
HCC4071B
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/24

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Product Details

Description



Features:

MEDIUM-SPEED OPERATION tPLH,tPHL =
   60ns. (typ.) AT VDD = 10V
QUIESCENT CURRENT SPECIFIED TO 20V
   FOR HCC DEVICE
5V, 10V AND 15V PARAMETRIC RATINGS
INPUT CURRENT OF 100nA AT 18V AND
   25°C FOR HCC DEVICE
100% TESTEDFOR QUIESCENT CURRENT
MEETSALLREQUIREMENTSOF JEDECTEN-
   TATIVE STANDARD No
13A, "STANDARD
   SPECIFICATIONS FOR DESCRIPTION OF "B"
   SERIES CMOS DEVICES"


Pinout

Connection Diagram


Specifications

Symbol
Parameter
Value
Unit
VDD*
 Supply Voltage : HCC Types
                           HCF Types
0.5 to + 20
0.5 to + 18
V
V
Vi
Input Voltage
0.5 to VDD + 0.5
V
II
 DC Input Current (any one input)
± 10
mA
Ptot
 Total Power Dissipation (per package)
Dissipation per Output Transistor
for Top = Full Package-temperature Range
200
100
mW
mW
Top
Operating Temperature : HCC Types
                                        HCF Types
55 to + 125
40to+85
°C
°C
Tstg
 Storage Temperature
65 to + 150
°C



Description

In the HCC/HCF4071B, 4072B and 4075B   series , the HCC4071B/4072B and 4075B (extended temperature range) and HCF4071B/4072B and 4075B (intermediate temperature range) are monolithic integrated circuits, available in 14-lead dual in-line plastic or ceramic package and plastic micropackage.

The HCC/HCF4071B, 4072B and 4075B OR gates provide the system designer with direct implementation of the positive-logic OR function and supplement the existing family of COS/MOSgates.




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