HCC4034B

Specifications

Symbol	Parameter	Value	Unit
VDD*	Supply Voltage :HCC Types HCF Types	0.5 to + 20 0.5 to + 18	V V
Vi	Input Voltage	0.5 to VDD + 0.5	V V
II	DC Input Current (any one input)	± 10	mA
Pto t	Total Power Dissipation (per package) Dissipation per Output Transistor for To p = Full Package-temperature Range	200 100	mW mW
Top	Operating Temperature : HCC Types HCF Types	55 to + 125 40 to + 85	°C °C
Ts tg	Storage Temperature	65 to + 150	°C

Description

The HCC/HCF4034B  (extended temperature range and intermediate temperature range) are monolithic integrated circuits, available in 24-lead dual in-line plastic or ceramic package and plastic micro package. The HCC/HCF4034B is a static eight-stage parallel-or serial-input parallel-output register. It can be used to : 1) bidirectionally transfer parallel information between two buses ; 2) convert serial data to parallel form and direct the parallel data to either of twobuses ; 3) store (recirculate) parallel data, or 4) accept parallel datafrom either of two buses and convert that data to serial form. Inputs that control the operations include a single-phase CLOCK (CL), A DATA ENABLE (AE), ASYNCHRONOUS/ SYNCHRONOUS (A/S), A-BUS-TOB- BUS/B-BUS-TO-A-BUS (A/B), and PARA LLEL/ SERIAL (P/S). Data inputs of HCC/HCF4034B  include 16 bidirectional parallel data lines of which the eight Adata lines are inputs (3-state outputs) and the Bdata lines are outputs (inputs) depending on the signal level on the A/B input. In addition, an input for SERIAL DATAisnalso provided. All register stages are D typemas ters lave flip-flops withseparate master and slave clock inputs generated internally to allow synchronous or asynchronous data transfer from master to slave. Isol  ation from external noise and the effects of loading is provided by output buffering.
PARALLEL OPERATION A high P/S input signal allows data transfer into the register via the parallel data lines synchronously with the positive transition of the clock provided the A/S input is low. If the A/S input of HCC/HCF4034B is high the transfer is independent of the clock. The direction of data flow is controlled by the A/B input. When this signal is high the A data lines are inputs (and B data lines are outputs) ; a low A/B signal reverses the direction of data flow. The AE-input is an additional feature which allows many registers to feed data to acommon bus. The ADATA lines of HCC/HCF4034B are enabled only when this signal is high. Data storage through recirculation of data in each register stage is accomplished by making the A/B signal high and the AE signal low.
SERIALOPERATION AlowP/S signal allows serial data to transfer into the register synchronously with the positive transition of the clock. The A/Sinput is inte rnally disabled whenthe register is in the serial mode (asynchronous serial operation is not allowed). The serial data appears as output data on either the B lines (when A/B is high) or the A lines (whenA/B is low andthe AE signal is high). Register expansion can be accomplished by simply cascading HCC/HCF4034B packages.