HCC4029B

Features:

`MEDIUM SPEED OPERATION - 8MHz (typ.)@ CL = 50pF AND VDD-VSS = 10V
`MULTI-PACKAGE PARALLEL CLOCKINGFOR SYNCHRONOUSHIGH SPEED OUTPUT RESPONSE OR RIPPLE CLOCKING FOR SLOW CLOCK INPUT RISE AND FALL TIMES
`"PRESET ENABLE" AND INDIVIDUAL"JAM"INPUTS PROVIDED`BINARY OR DECADE UP/DOWN COUNTING
`BCD OUTPUTS IN DECADEMODE
`STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS
`5V, 10V, AND 15V PARAMETRIC RATINGS INPUT CURRENTOF 100nA AT 18V AND 25°C FOR HCC DEVICE
`QUIESCENT CURRENT SPECIFIED TO 20V FOR HCC DEVICE`100% TESTEDFOR QUIESCENT CURRENT`MEETSALLREQUIREMENTSOFJEDECTENTATIVE STANDARD No. 13A, "STANDARD SPECIFICATIONS FOR DESCRIPTION OF "B" SERIESCMOS DEVICES"

Specifications

Symbol	Rating	Value	Unit
VDD*	Supply Voltage : HCC Types HCF Types	0.5 to + 20 0.5 to + 18	V V
Vi	Input Voltage	0.5 to VDD + 0.5	V
II	DC Input Current (any one input)	± 10	mA
Ptot	Total Power Dissipation (per package) Dissipation per Output Transistor for Top = Full Package-temperature Range	200 100	mW mW
Top	Operating Temperature : HCC Types HCF Types	55 to + 125 40 to + 85	°C °C
Tstg	Storage Temperature	65 to + 150	°C

Stressesabove those listedunder "Absolute Maximum Ratings"may cause permanent damage to thedevice. This isa stress ratingonly and functional
operation of the device at these or any other conditions above those indicated in theoperational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for external periods may affect device reliability.
All voltage values are referred to VSS pin voltage.


Description

The HCC4029B (extended temperature range) and HCF4029B (intermediate temperature range) are monolithic integrated circuit, available in 16-lead dual in-line plastic or ceramic package and plastic micro package. The HCC/HCF4029B consists of a four-stage binary or BCD-decade up/down counter with provisions for look-ahead carry in both counting modes. The inputs consist of a single CLOCK, CARRY-IN (CLOCK ENABLE) , BINARY/DECADE, UP/DOWN, PRESET ENABLE, and four individual JAM signals. Q1, Q2, Q3, Q4 and a CARRY OUT signal are provided as outputs. Ahigh PRESET ENABLE signal allows information on the JAM INPUTS to preset the counter to any state asynchronously with the clock. A low on each JAM line, when the PRESET-ENABLE signal is high, resets the counter to its zero count. The counter is advanced one count at the positive transition of the clock when the CARRY-IN and PRESET ENABLE signals, are low. Advancement in HCC/HCF4029B  is inhibited when the CARRY-IN or PRESET ENABLE signals are high. The CARRYOUT signal is normally high and goes low when the counter reaches itsmaximum count in the UPmode or the minimum count in the DOWN mode provided the CARRY-IN signal is low. The CARRY-IN signal in the low state can thus be considered a CLOCK ENABLE. The CARRY-IN terminal must be connected toVSS whennot in use. Binary counting is accomplished when the BINARY/DECADE input is high ; the counter counts in the decade mode when the BINARY/DECADE input is low. The counter counts Up when to UP/DOWN INPUT is high, and Down when the UP/DOWN INPUT is low. Multiple packages of HCC/HCF4029B can be connected in either a parallelclocking or a ripple-clocking arrangement as shown in cascading counter packages. Parallel clocking of HCC/HCF4029B  provides synchronous control and hence faster response from all counting outputs. Ripple-clocking allows for longer clock input rise and fall times.