Specifications Symbol Parameter Value Unit VDD* Supply Voltage :HCC Types HCF Types 0.5 to + 20 0.5 to + 18 VV Vi Input Voltage 0.5 to VDD + 0.5 V II DC Input Current (any one input) ± 10 mA Ptot Total Power Dissipation (per package)Dissipation per Output T...
HCC4022B: Specifications Symbol Parameter Value Unit VDD* Supply Voltage :HCC Types HCF Types 0.5 to + 20 0.5 to + 18 VV Vi Input Voltage 0.5 to VDD + 0.5 V II DC Input Curren...
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Symbol | Parameter | Value | Unit |
VDD* | Supply Voltage :HCC Types HCF Types |
0.5 to + 20 0.5 to + 18 |
V V |
Vi | Input Voltage | 0.5 to VDD + 0.5 | V |
II | DC Input Current (any one input) | ± 10 | mA |
Ptot | Total Power Dissipation (per package) Dissipation per Output Transistor for Top = Full Package-temperature Range |
200 100 |
mW mW |
Top | Operating Temperature : HCC Types HCF Types |
55 to + 125 40 to + 85 |
°C °C |
Tstg | Storage Temperature | 65 to + 150 | °C |
In the HCC/HCF4017B and HCC/HCF4022B series, the HCC4017B/4022B (extended temperature range) and HCF4017B/4022B (intermediate temperature range) are monolithic integrated circuits, available in 16-lead dual in-line plastic or ceramic package and plastic micro package.
The HCC/HCF4017B and HCC/HCF4022B are 5- stage and 4-stage Johnson counters having 10 and 8 decoded outputs, respectively. Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT signal. Schmitt trigger action in theCLOCKinput circuit providespulse shaping that allows unlimited clock input pulse rise and fall times. These counters are advanced one count at the positive clock signal transition if the CLOCK INHIBIT signal is low. Counter advancement via the clock line is inhibited when the CLOCKINHIBIT signal is high. Ahigh RESET signal clears the counter to its zero count. Use of the Johnson decade counter configuration permits high-speed operation, 2-input decimal-decode gating, and spike-free decoded outputs. Anti-lock gating is provided, thus assuring proper counting sequence. The decoded outputs are normally low and go high only at their respective decoded time slot. Each decoded output remains high for one full clock cycle. A CARRY-OUT signal completes one cycle every 10 clock input cycles in the HCC/HCF4017B and HCC/HCF4022B and is used to ripple-clock the succeeding device in a multi-device counting chain.