Specifications Symbol Parameter Value Unit VDD* Supply Voltage :HCC Types HCF Types 0.5 to + 20 0.5 to + 18 VV Vi Input Voltage 0.5 to VDD + 0.5 V II DC Input Current (any one input) ± 10 mA Ptot Total Power Dissipation (per package)Dissipation per Output T...
HCC40194B: Specifications Symbol Parameter Value Unit VDD* Supply Voltage :HCC Types HCF Types 0.5 to + 20 0.5 to + 18 VV Vi Input Voltage 0.5 to VDD + 0.5 V II DC Input Curren...
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Symbol | Parameter | Value | Unit |
VDD* | Supply Voltage :HCC Types HCF Types |
0.5 to + 20 0.5 to + 18 |
V V |
Vi | Input Voltage | 0.5 to VDD + 0.5 | V |
II | DC Input Current (any one input) | ± 10 | mA |
Ptot | Total Power Dissipation (per package) Dissipation per Output Transistor for Top = Full Package-temperature Range |
200 100 |
mW mW |
Top | Operating Temperature : HCC Types HCF Types |
55 to + 125 40 to + 85 |
°C °C |
Tstg | Storage Temperature | 65 to + 150 | °C |
In the HCC/HCF 40104B series, the HCC40104B, HCC40194B, (extended temperature range) and the HCC40104B, HCF40194B (intermediate temperature range) are monolithic integrated circuits, available in 16-lead dual in-line plastic or ceramic package and plastic micro package. The HCC/HCF 40104B is a universal shift register featuring parallel inputs, parallel outputs, SHIFT RIGHTand SHIFTLEFT serial inputs, and a high-impedance third output state allowing the device to be used in bus-organized systems. In the parallel-load mode (S0 and S1 are high), data is loaded into the associated flip-flop and appears at the output after the positive transition of the CLOCK input. During loading, serial data flow is inhibited. Shift-right and shift-left are accomplished synchronously on the positive clock edge with serial data entered at the SHIFT RIGHT and SHIFT LEFT serial inputs, respectively. Clearing the register is accomplished by setting both mode controls low and clocking the register. When the output enable input is low, all outputs assume the high impedance state. The HCC/HCF40194B is a universal shift register featuringparallel inputs, parallel outputsSHIFT RIGHTand SHIFT LEFT serial inputs, and a direct overriding clear input. In the parallel-load mode (S0 and S1 are high), data is loaded into the associated flip-flop and appears at the output after the positive transition of the CLOCK input. During loading, serial data flow is inhibited. Shift right and shift left are accomplished synchronously on the positive clock edge with data entered at the SHIFT RIGHT and SHIFT LEFT serial inputs, respectively. Clocking of the register is inhibited when bothmode control inputs are low. When low, theRESET input resets all stages and forces all outputs low. The HCC/HCF40194B is similar to industry types 340194 and MC40194.