HCC40108B

Features:

`FOUR 4-BIT REGISTERS
`ONE INPUT AND TWO OUTPUT BUSES 
`UNLIMITED EXPANSION IN BIT AND WORD DIRECTION
`DATA LINES HAVE LATCHED INPUTS
`3-STATE OUTPUTS
`SEPARATE CONTROL OF EACH BUS, ALLOWING SIMULTANEOUS INDEPENDET READING AND ANY OF FOUR REGISTERS ON BUS A AND BUS B AND INDEPENDENT WRITING INTOANY ANY OF THE FOURREGISTERS
`40108B IS PINCOMPATIBLE WITH INDUSTRY TYPE MC14580
`STANDARDIZED, SYMMETRICAL OUTPUT CHARACTERISTICS
`QUIESCENT CURRENT SPECIFIED AT 20V FOR HCC DEVICE
`5V, 10V AND 15V PARAMETRIC RATINGS
`INPUTCURRENTOF100nA AT18VAND 25 FOR HCC DEVICE
`100% TESTEDFOR QUIESCENT CURRENT
`MEETSALLREQUIREMENTSOFJEDECTENTATIVE STANDARD No 13a, "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIESCMOS DEVICES"


Pinout




Specifications

Symbol	Parameter	Value	Unit
VDD*	Supply Voltage :HCC Types HCF Types	0.5 to + 20 0.5 to + 18	V V
Vi	Input Voltage	0.5 to VDD + 0.5	V
II	DC Input Current (any one input)	± 10	mA
Ptot	Total Power Dissipation (per package) Dissipation per Output Transistor for Top = Full Package-temperature Range	200 100	mW mW
Top	Operating Temperature : HCC Types HCF Types	55 to + 125 40 to + 85
Tstg	Storage Temperature	65 to + 150

Description

In the HCC/HCF40108B series, the HCC40108B (extended temperature range) and HCF40108B (intermediate temperature range) are monolithic integrated circuits, available in 24 lead dual in line plastic or ceramic packageand plastic micropackage. The HCC/HCF40108B is a 4 X 4 multiport register containing four 4-bit register, write address decoder, two separate read address decoders, and two 3-state output buses. When the ENABLE input is low, the corresponding output bus is switched, independently of the clock, to a high impedance state. The high impedance third state provides the outputs with the capability of being connected to the bus lines in a bus organized system without the need for interface or pull-up components.

When the WRITE ENABLE input is high, all data input lines of HCC/HCF40108B  are latched on the positive transition of the CLOCK and the data is entered into the word selected by the write address lines. When WRITE ENABLE is low, the CLOCK is inhibited and no new data is netered. In either case, the contents of any word may be accessed via the read address lines independent of the state of the CLOCK input.