HCC40103B

Features:

`SYNCHRONOUS OR ASYNCHRONOUS PRESET
`MEDIUM-SPEED OPERATION : fCL = 3.6MHz (TYP.) @ VDD = 10V
`CASCADABLE
`QUIESCENT CURRENT SPECIFIED TO 20V FOR HCC DEVICE
`5V, 10V AND 15V PARAMETRIC RATINGS
`INPUT CURRENTOF100 nA AT 18V AND25 FOR HCC DEVICE
`100% TESTEDFOR QUIESCENT CURRENT
`MEETSALLREQUIREMENTSOFJEDECTENTATIVE STANDARD No
`13 A, "STANDARD SPECIFICATIONS FOR DESCRIPTION OF "B"SERIESCMOS DEVICES"


Pinout




Specifications

Symbol	Parameter	Value	Unit
VDD*	Supply Voltage :HCC Types HCF Types	0.5 to + 20 0.5 to + 18	V V
Vi	Input Voltage	0.5 to VDD + 0.5	V
II	DC Input Current (any one input)	± 10	mA
Ptot	Total Power Dissipation (per package) Dissipation per Output Transistor for Top = Full Package-temperature Range	200 100	mW mW
Top	Operating Temperature : HCC Types HCF Types	55 to + 125 40 to + 85
Tstg	Storage Temperature	65 to + 150

Description

In the HCC/HCF40102B, HCC/HCF40103B series, the HCC40102B, HCC40103B, (extended temperature range) and the HCF40102B, HCF40103B (intermediate temperature range) aremonolithic integrated circuits, available in 16-lead dual in-line plastic or ceramic package. The HCC/HCF40102B, HCC/HCF40103B  consist of an 8-stage synchronous down counterwith asingle output which isactivewhen the internal count is zero. The HCC/HCF40102B, HCC/HCF40103B  are configured as two cascaded 4-bit BCD counters, and the HCC/HCF40103B contains a single 8-bit binary counter. Each type has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All control inputs and the CARRY-OUT/ZERO-DETECT output are active-low logic. In normal operation, the counter is decremented by one count on each positive transition of the CLOCK. Counting is inhibited when the CARRY-IN/COUNTER ENABLE (CI/CE) input is high. The CARRY-OUT/ZERO-DETEC (CO/ZD) output goes low when the count reaches zero if the CI/CE input is low, and remains low for one full clock period. When the SYNCHRONOUS PRESET-ENABLE (SPE) input is low, data at the JAM input is clocked into the counter on the next positive clock transition regardless of the state of the CI/CE input. When the ASYNCHRONOUS PRESET-ENABLE (APE) input is low, data at the JAM inputs is asynchronously forced into the counter regardless of the state of the SPE, CI/CE, or CLOCK inputs. JAM inputs JO-J7 represent two 4-bit BCD words for the HCC/HCF40102B and a single 8-bit binary word for the HCC/HCF40103B.

When the CLEAR (CLR) input is low, the counter is asynchronously cleared to its maximum count (9910 for the HCC/HCF40102B and 25510 for theHCC/HCF40103B) regardless of the state of any other input. The precedence relationship between control input is indicated in the truth table. If all control inputs are high at the tieme of zero count, the counters will jump to the maximum count, giving a counting sequence of 100 or 256 clock pulses long. The HCC/HCF40102B, HCC/HCF40103B  may be cascaded using the CI/CE input and the