HCC40100B

Features:

`FULLY STATIC OPERATION
`SHIFT LEFT/SHIFT RIGHT CAPABILITY
`MULTIPLE PACKAGE CASCADING
`RECIRCULATE CAPABILITY
`LIFO OR FIFO CAPABILITY
`STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS
`QUIESCENT CURRENT SPECIFIED AT 20V FOR HCC DEVICE
`5V, 10V, AND 15V PARAMETRIC RATINGS
`INPUT CURRENTOF 100nA AT 18V AND 25°C FOR HCC DEVICE
`100% TESTEDFOR QUIESCENT CURRENT
`MEETSALLREQUIREMENTSOFJEDECTENTATIVE  STANDARD No. 13A, "STANDARD SPECIFICATIONS FOR DESCRIPTION OF "B"SERIESCMOS DEVICES"


Pinout




Specifications

Symbol	Parameter	Value	Unit
VDD*	Supply Voltage :HCC Types HCF Types	0.5 to + 20 0.5 to + 18	V V
Vi	Input Voltage	0.5 to VDD + 0.5	V
II	DC Input Current (any one input)	± 10	mA
Ptot	Total Power Dissipation (per package) Dissipation per Output Transistor for Top = Full Package-temperature Range	200 100	mW mW
Top	Operating Temperature : HCC Types HCF Types	55 to + 125 40 to + 85
Tstg	Storage Temperature	65 to + 150

Description

In the  HCC/HCF40100B  series, the HCC40100B (extended temperature range) and HCF40100B (intermediate temperature range) are monolithic integrated circuits, available in 16-lead dual in-line plastic or ceramic package and plastic micro package. The HCC/HCF40100B is a 32-stage shift register containing 32 D-type masterslave flip-flops. The data of HCC/HCF40100B present at the SHIFTRIGHT INPUT is transferred into the first register stage synchronously with the positive CLOCKedge, provided the LEFT/RIGHT CONTROL is at a low level, the RECIRCULATE CONTROL is at a high level, and the CLOCK INHIBIT is low. If the LEFT/RIGHT CONTROL is at a high level and the RECIRCULATE CONTROL is also high, data at the SHIFT-LEFT INPUT is transferred into the 32nd register stage synchronously with the positive CLOCK transition, provided the CLOCK INHIBIT is low. The state of the LEFT/RIGHT CONTROL, RECIRCULATE CONTROL, and CLOCK INHIBIT should not be changed when theCLOCKishigh. Data is shifted one stage left or one stage right depending on the state of the LEFT/RIGHT CONTROL, synchronously with the positive CLOCK edge. Data clocked into the first or 32nd register states is available at the SHIFT-LEFT or SHIFT-RIGHT OUTPUT respectively, on the next negative CLOCK transition (see Data Transfer Table). No shifting occurs on the positive CLOCKedge if the CLOCK INHIBIT line is at a high level.Withthe RECIRCULATE CONTROL low,