HC2509C

Features:

`Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications
`Supports PC-100 and Meets "PC100 SDRAM registered DIMM Specification Rev. 1.2"
`Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs
`No External RC Network Required
`External Feedback (FBIN) Pin is Used to Synchronize the Outputs to the Clock Input
`Separate Output Enable for Each Output Bank
`Operates at 3.3 V Vcc
`125 MHz Maximum Frequency
`On-chip Series Damping Resistors
`Support Spread Spectrum Clock(SSC) Synthesizers
`ESD Protection Exceeds 3000 V per MIL-STD- 883, Method 3015 ; Exceeds 350 V Using Machine Model ( C = 200 pF, R = 0 )
`Latch-Up Performance Exceeds 400 mA per JESD 17
`Packaged in Plastic 24-Pin Thin Shrink Small- Outline Package


Pinout




Specifications

Symbols	Parameter	Value	Unit	Conditions
Vcc	Supply Voltage Range	-0.5 to 4.6	V
VI	Input Voltage Range	-0.5 to 6.5	V
Vo	Voltage Range applied to any input in the high or low state	-0.5 to Vcc+0.5	V
IIK	Input Clamp Current	±50	mA	VI <0 or VI >0
IOK	Output Clamp Current	±50	mA	Vo<0 or Vo> Vcc
Io	Continuous Output Current	±50	mA	Vo=0 to Vcc
PMAX	Maximum Power Dissipaiton	0.7	W
Tstg	Storage Temperature Range	-65 to 150

Description

The HC2509C is a low-skew, low jitter, phase-locked loop(PLL) clock driver, distributing high frequency clock signals for SDRAM.

The HC2509C operates at 3.3V Vcc and provides integrated series-damping resistors that make it ideal for driving point-to-point loads. The propagation delay from the CLK input to any clock output is nearly zero.

One bank of five outputs and one bank of four outputs provide nine low-skew and low-jitter clocks. Each bank of outputs can be enabled or disabled separately via the control inputs (1G and 2G). Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. The HC2509C is specially designed to interface with high speed SDRAM applications in the range of 25MHz to 125MHz and includes an internal RC network which provides excellent jitter characteristics and eliminates the needs for external components.

For the test purpose, the PLL can be bypassed by strapping AVcc to ground. The HC2509C is characterized for operation from 0 to 85.