HB52F649E1-75B

Features:

• Fully compatible with : JEDEC standard outline 8-byte DIMM
• 168-pin socket type package (dual lead out) Outline: 133.35 mm (Length) × 43.18 mm (Height) × 4.00 mm (Thickness) Lead pitch: 1.27 mm
• 3.3 V power supply
• Clock frequency: 133 MHz (max)
• LVTTL interface
• Data bus width: × 72 ECC
• Single pulsed RAS
• 4 Banks can operates simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• Programmable burst length: 1/2/4/8
• 2 variations of burst sequence Sequential Interleave
• Programmable CE latency : 4 (133 MHz)
                                            : 3 (100 MHz)
• Byte control by DQMB
• Refresh cycles: 8192 refresh cycles/64 ms
• 2 variations of refresh Auto refresh Self refresh


Specifications

Parameter	Symbol	Value	Unit	Note
Voltage on any pin relative to VSS	VT	0.5 to VCC + 0.5 ( 4.6 (max))	V	1
Supply voltage relative to VSS	VCC	0.5 to +4.6	V	1
Short circuit output current	IOUT	50	mA
Power dissipation	PT	18.0	W
Operating temperature	Topr	0 to +65
Storage temperature	Tstg	50 to +100

Description

The HB52F649E1 belongs to 8-byte DIMM (Dual In-line Memory Module) family, and has been developed as an optimized main memory solution for 8-byte processor applications. The HB52F649E1 is a 64M × 72 × 1-bank Synchronous Dynamic RAM Registered Module, mounted 18 pieces of 256-Mbit SDRAM (HM5225405BTT) sealed in TSOP package, 1 piece of PLL clock driver, 3 pieces of register driver and 1 piece of serial EEPROM (2-kbit) for Presence Detect (PD). An outline of the HB52F649E1 is 168-pin socket type package (dual lead out). Therefore, the HB52F649E1 makes high density mounting possible without surface mount technology. It provides common data inputs and outputs. Decoupling capacitors are mounted beside each TSOP on the module board.