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GS8342T08

Features: • Simultaneous Read and Write SigmaCIO™ Interface• Common I/O bus• JEDEC-standard pinout and package• Double Data Rate interface• Byte Write (x36 and x18) and Nybble Write (x8) function• Burst of 2 Read and Write• 1.8 V +100/100 mV core pow...

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SeekIC No. : 004356043 Detail

GS8342T08: Features: • Simultaneous Read and Write SigmaCIO™ Interface• Common I/O bus• JEDEC-standard pinout and package• Double Data Rate interface• Byte Write (x36 and x1...

GS8342T08 Data Sheet

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Part Number:
GS8342T08
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Simultaneous Read and Write SigmaCIO™ Interface
• Common I/O bus
• JEDEC-standard pinout and package
• Double Data Rate interface
• Byte Write (x36 and x18) and Nybble Write (x8) function
• Burst of 2 Read and Write
• 1.8 V +100/100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation with self-timed Late Write
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
• Pin-compatible with present 9Mb and 18Mb and future 72Mb and 144Mb devices


Specifications

Symbol Description Value Unit
VDD

VDDQ

VREF

VI/O

VIN

IIN

IOUT

TJ

TSTG		 Voltage on VDD Pins

Voltage in VDDQ Pins

Voltage in VREF Pins

Voltage on I/O Pins

Voltage on Other Input Pins

Input Current on Any Pin

Output Current on Any I/O Pin

Maximum Junction Temperature

Storage Temperature		 0.5 to 2.9

0.5 to VDD

0.5 to VDDQ

0.5 to VDDQ +0.5 ( 2.9 V max.)

0.5 to VDDQ +0.5 ( 2.9 V max.)

+/100

+/100

125

55 to 125		 V

V

V

V

V

mA dc

mA dc

°C

°C
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect reliability of this component.


Description

The GS8342T08/09/18/36E are built in compliance with the SigmaCIO DDR-II SRAM pinout standard for Common I/O synchronous SRAMs. They are 37,748,736-bit (36Mb) SRAMs. The GS8342T08/09/18/36E SigmaCIO SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.




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