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GS8342S08

Features: • Simultaneous Read and Write SigmaSIO™ Interface• JEDEC-standard pinout and package• Dual Double Data Rate interface• Byte Write controls sampled at data-in time• DLL circuitry for wide output data valid window and future frequency scaling• Burs...

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SeekIC No. : 004356038 Detail

GS8342S08: Features: • Simultaneous Read and Write SigmaSIO™ Interface• JEDEC-standard pinout and package• Dual Double Data Rate interface• Byte Write controls sampled at data-in ...

GS8342S08 Data Sheet

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Part Number:
GS8342S08
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Simultaneous Read and Write SigmaSIO™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• DLL circuitry for wide output data valid window and future frequency scaling
• Burst of 2 Read and Write
• 1.8 V +100/100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ mode pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
• Pin-compatible with future 72Mb and 144Mb devices


Specifications

Symbol Description Value Unit
VDD

VDDQ

VREF

VI/O

VIN

IIN

IOUT

TJ

TSTG		 Voltage on VDD Pins

Voltage in VDDQ Pins

Voltage in VREF Pins

Voltage on I/O Pins

Voltage on Other Input Pins

Input Current on Any Pin

Output Current on Any I/O Pin

Maximum Junction Temperature

Storage Temperature		 0.5 to 2.9

0.5 to VDD

0.5 to VDDQ

0.5 to VDDQ +0.5 ( 2.9 V max.)

0.5 to VDDQ +0.5 ( 2.9 V max.)

+/100

+/100

125

55 to 125		 V

V

V

V

V

mA dc

mA dc

°C

°C

Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect reliability of this component.




Description

GS8342S08/09/18/36 are built in compliance with the SigmaSIO-II SRAM pinout standard for Separate I/O synchronous SRAMs. They are 37,748,736-bit (36Mb) SRAMs. GS8342S08/09/18/36 are the first in a family of wide, very low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.




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