Features: • NBT (No Bus Turn Around) functionality allows zero wait Read-Write-Read bus utilization; fully pin-compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs
• FT pin for user-configurable flow through or pipeline operation
• IEEE 1149.1 JTAG-compatible Boundary Scan
• ZQ mode pin for user-selectable high/low output drive
• 2.5 V or 3.3 V +10%/5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 119- and 209-bump BGA packageApplicationThe GS8324Z18/36/72 is a 37,748,736-bit high performance 2-die synchronous SRAM module with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.
Specifications
| Symbol |
Description |
Value |
Unit |
| VDD |
Voltage on VDD Pins |
0.5 to 4.6 |
V |
| VDDQ |
Voltage in VDDQ Pins |
0.5 to 4.6 |
V |
| VCK |
Voltage on Clock Input Pin |
0.5 to 6 |
V |
| V I/O |
Voltage on I/O Pins |
0.5 to VDDQ +0.5 ( 4.6 V max.) |
V |
| VIN |
Voltage on Other Input Pins |
0.5 to VDD +0.5 ( 4.6 V max.) |
V |
| IIN |
Input Current on Any Pin |
+/20 |
mA |
| IOUT |
Output Current on Any I/O Pin |
+/20 |
mA |
| PD |
Package Power Dissipation |
1.5 |
W |
| TSTG |
Storage Temperature |
55 to 125 |
oC |
| TBIAS |
Temperature Under Bias |
55 to 125 |
oC |
DescriptionThe GS8324Z18/36/72 is a 37,748,736-bit high performance 2-die synchronous SRAM module with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the GS8324Z18/36/72 now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.
Addresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edgetriggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter GS8324Z18/36/72 may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function of GS8324Z18/36/72 need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.
The function of the Data Output register GS8324Z18/36/72 can be controlled by the user via the FT mode . Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising-edge-triggered Data Output Register.
Byte write operation of GS8324Z18/36/72 is performed by using Byte Write enable(BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.
The ZQ pin allows of GS8324Z18/36/72 selection between high drive strength (ZQ low) for multi-drop bus applications and normal drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.
Low power (Sleep mode)of GS8324Z18/36/72 is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.
The GS8324Z18/36/72 operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 3.3 V and 2.5 V compatible.
GS8324Z36C Data Sheet
