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GS8180DV18D-100

Features: • Simultaneous Read and Write SigmaQuad™ Interface• JEDEC-standard pinout and package• Dual DoubleData Rate interface• Byte Write controls sampled at data-in time• Burst of 4 Read and Write• 2.5 V +100/100 mV core power supply• 1.5 V or 1.8...

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SeekIC No. : 004355888 Detail

GS8180DV18D-100: Features: • Simultaneous Read and Write SigmaQuad™ Interface• JEDEC-standard pinout and package• Dual DoubleData Rate interface• Byte Write controls sampled at data-in ...

GS8180DV18D-100 Data Sheet

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Part Number:
GS8180DV18D-100
Supply Ability:
5000

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  • 1~5000
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  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual DoubleData Rate interface
• Byte Write controls sampled at data-in time
• Burst of 4 Read and Write
• 2.5 V +100/100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ mode pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
• Pin-compatible with future 36Mb, 72Mb, and 144Mb devices
• Pb-Free 165-bump BGA package available


Specifications

Symbol Description Value Unit
VDD Voltage on VDD Pins 0.5 to 3.6 V
VDDQ Voltage in VDDQ Pins

0.5 to 3.6

 V
VI/O Voltage on I/O Pins 0.5 to VDDQ +0.5 ( 3.6 V max.) V
VIN Voltage on Other Input Pins 0.5 to VDDQ +0.5 ( 3.6 V max.) V
IIN Input Current on Any Pin +/100 mA dc
IOUT Output Current on Any I/O Pin +/100 mA dc
TJ Maximum Junction Temperature 125 °C
TSTG Storage Temperature 55 to 125 °C
VREF Voltage in VREF Pins 0.5 to VDDQ V
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect reliability of this component.


Description

GS8180DV18 is built in compliance with the SigmaQuad SRAM pinout standard for Separate I/O synchronous SRAMs. GS8180DV18 is18,874,368-bit (18Mb) SRAMs. These are the first in a family of wide, very low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.

SigmaQuad SRAMs GS8180DV18 are offered in a number of configurations.ome emulate and enhance other synchronous separate I/O SRAMs. A higher performance SDR (Single Data Rate) Burst of 2 version is also offered. The logical differences between the protocols employed by these RAMs GS8180DV18 hinge mainly on various combinations of address bursting, output data registering, and write cueing. Along with the Common I/O family of SigmaRAMs, the SigmaQuad family of SRAMs allows a user to implement the interface protocol best suited to the task at hand




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