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GS8170LW36AC-333

Features: • Late Write mode, Pipelined Read mode• JEDEC-standard SigmaRAM™ pinout and package• 1.8 V +150/100 mV core power supply• 1.8 V CMOS Interface• ZQ controlled user-selectable output drive strength• Dual Cycle Deselect• Burst Read and Write o...

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SeekIC No. : 004355877 Detail

GS8170LW36AC-333: Features: • Late Write mode, Pipelined Read mode• JEDEC-standard SigmaRAM™ pinout and package• 1.8 V +150/100 mV core power supply• 1.8 V CMOS Interface• ZQ contr...

GS8170LW36AC-333 Data Sheet

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Part Number:
GS8170LW36AC-333
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Late Write mode, Pipelined Read mode
• JEDEC-standard SigmaRAM™ pinout and package
• 1.8 V +150/100 mV core power supply
• 1.8 V CMOS Interface
• ZQ controlled user-selectable output drive strength
• Dual Cycle Deselect
• Burst Read and Write option
• Fully coherent read and write pipelines
• Echo Clock outputs track data output drivers
• Byte write operation (9-bit bytes)
• 2 user-programmable chip enable inputs
• IEEE 1149.1 JTAG-compliant Serial Boundary Scan
• 209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package
• Pin-compatible with future 36Mb, 72Mb, and 144Mb devices
• Pb-Free 209-bump BGA package available


Specifications

Symbol
Description
Value
Unit
VDD
Voltage on VDD Pins
0.5 to 2.5
V
VDDQ
Voltage on VDDQ Pins
0.5 to VDD
V
VI/O
Voltage on I/O Pins
0.5 to VDDQ + 0.5 ( 2.5 V max.)
V
VIN
Voltage on Other Input Pins
0.5 to VDDQ + 0.5 ( 2.5 V max.)
V
IIN
Input Current on Any Pin
+/100
mA dc
IOUT
Output Current on Any I/O Pin
+/100
mA dc
TJ
Maximum Junction Temperature
125
TSTG
Storage Temperature
55 to 125
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect reliability of this component.


Description

GS8170LW36/72A SigmaRAMs are built in compliance with the SigmaRAM pinout standard for synchronous SRAMs. GS8170LW36/72A are 18,874,368-bit (18Mb) SRAMs. This family of wide, very low voltage CMOS I/O SRAMs is designed to operate at the speeds needed to implement economical high performance networking systems.

RAMs GS8170LW36/72A are offered in a number of configurations including Late Write, Double Late Write, and Double Data Rate (DDR). The logical differences between the protocols employed by these RAMs mainly involve various approaches to write cueing and data transfer rates. The RAM™ GS8170LW36/72A family standard allows a user to implement the interface protocol best suited to the task at hand.




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