GS8162Z72C

The GS8162Z18(B/D)/36(B/D)/72(C) is an 18MbitSynchronous Static SRAM. GSI's NBT SRAMs, like ZBT,NtRAM, NoBL or other pipelined read/double late write orflow through read/single late write SRAMs, allow utilizationof all available bus bandwidth by eliminating the need to insertdeselect cycles when the GS8162Z18(B/D)/36(B/D)/72(C) is switched from read to writecycles.

Because GS8162Z18(B/D)/36(B/D)/72(C) is a synchronous device, address, data inputs, andread/write control inputs are captured on the rising edge of theinput clock. Burst order control (LBO) must be tied to a powerrail for proper operation. Asynchronous inputs of GS8162Z18(B/D)/36(B/D)/72(C) include theSleep mode enable (ZZ) and Output Enable. Output Enable canbe used to override the synchronous control of the outputdrivers and turn the RAM's output drivers off at any time.Write cycles are internally self-timed and initiated by the risingedge of the clock input. GS8162Z18(B/D)/36(B/D)/72(C) feature eliminates complex offchipwrite pulse generation required by asynchronous SRAMsand simplifies input signal timing.

The GS8162Z18(B/D)/36(B/D)/72(C) may be configured bythe user to operate in Pipeline or Flow Through mode.Operating as a pipelined synchronous device, in addition to therising-edge-triggered registers that capture input signals, the GS8162Z18(B/D)/36(B/D)/72(C) incorporates a rising edge triggered output register. Forread cycles, pipelined SRAM output data is temporarily storedby the edge-triggered output register during the access cycleand then released to the output drivers at the next rising edge ofclock.

The GS8162Z18(B/D)/36(B/D)/72(C) is implemented withGSI's high performance CMOS technology and is available ina JEDEC-standard 119-bump (x18 & x36), 165-bump (x18 &x36), or 209-bump (x72) BGA package.