GS8162Z36B

Features: • NBT (No Bus Turn Around) functionality allows zero waitRead-Write-Read bus utilization; fully pin-compatible withboth pipelined and flow through NtRAM™, NoBL™ andZBT™ SRAMs• 2.5 V or 3.3 V +10%/10% core power supply• 2.5 V or 3.3 V I/O supply• ...

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SeekIC No. : 004355862 Detail

GS8162Z36B: Features: • NBT (No Bus Turn Around) functionality allows zero waitRead-Write-Read bus utilization; fully pin-compatible withboth pipelined and flow through NtRAM™, NoBL™ andZBT...

floor Price/Ceiling Price

Part Number:
GS8162Z36B
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Features:

• NBT (No Bus Turn Around) functionality allows zero waitRead-Write-Read bus utilization; fully pin-compatible withboth pipelined and flow through NtRAM™, NoBL™ andZBT™ SRAMs
• 2.5 V or 3.3 V +10%/10% core power supply
• 2.5 V or 3.3 V I/O supply
• User-configurable Pipeline and Flow Through mode
• ZQ mode pin for user-selectable high/low output drive
• IEEE 1149.1 JTAG-compatible Boundary Scan
LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2M, 4M, and 8M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 119-, 165-, or 209-Bump BGA package





Specifications

Symbol Description Value Unit
VDD Voltage on VDD Pins 0.5 to 4.6 V
VDDQ Voltage in VDDQ Pins 0.5 to 4.6 V
VI/O Voltage on I/O Pins 0.5 to VDDQ +0.5 ( 4.6 V max.) V
VIN Voltage on Other Input Pins 0.5 to VDD +0.5 ( 4.6 V max.) V
IIN Input Current on Any Pin +/20 mA
IOUT Output Current on Any I/O Pin +/20 mA
PD Package Power Dissipation 1.5 W
TSTG Storage Temperature 55 to 125 oC
TBIAS Temperature Under Bias 55 to 125 oC





Description

The GS8162Z18(B/D)/36(B/D)/72(C) is an 18MbitSynchronous Static SRAM. GSI's NBT SRAMs, like ZBT,NtRAM, NoBL or other pipelined read/double late write orflow through read/single late write SRAMs, allow utilizationof all available bus bandwidth by eliminating the need to insertdeselect cycles when the GS8162Z18(B/D)/36(B/D)/72(C) is switched from read to writecycles.

Because it is a synchronous device, address, data inputs, andread/write control inputs are captured on the rising edge of theinput clock. Burst order control (LBO) must be tied to a powerrail for proper operation. Asynchronous inputs of GS8162Z18(B/D)/36(B/D)/72(C) include the Sleep mode enable (ZZ) and Output Enable. Output Enable canbe used to override the synchronous control of the outputdrivers and turn the RAM's output drivers off at any time.Write cycles are internally self-timed and initiated by the risingedge of the clock input. GS8162Z18(B/D)/36(B/D)/72(C) feature eliminates complex offchipwrite pulse generation required by asynchronous SRAMsand simplifies input signal timing.

The GS8162Z18(B/D)/36(B/D)/72(C) may be configured bythe user to operate in Pipeline or Flow Through mode.Operating as a pipelined synchronous device, in addition to therising-edge-triggered registers that capture input signals, the GS8162Z18(B/D)/36(B/D)/72(C) incorporates a rising edge triggered output register. Forread cycles, pipelined SRAM output data is temporarily storedby the edge-triggered output register during the access cycleand then released to the output drivers at the next rising edge ofclock.

The GS8162Z18(B/D)/36(B/D)/72(C) is implemented withGSI's high performance CMOS technology and is available ina JEDEC-standard 119-bump (x18 & x36), 165-bump (x18 &x36), or 209-bump (x72) BGA package.






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