Features: • FT pin for user-configurable flow through or pipeline operation• Dual Cycle Deselect (DCD) operation• IEEE 1149.1 JTAG-compatible Boundary Scan• 2.5 V or 3.3 V +10%/10% core power supply• 2.5 V or 3.3 V I/O supply• LBO pin for Linear or Interleaved B...
GS8161E18D-200: Features: • FT pin for user-configurable flow through or pipeline operation• Dual Cycle Deselect (DCD) operation• IEEE 1149.1 JTAG-compatible Boundary Scan• 2.5 V or 3.3 V +1...
SeekIC Buyer Protection PLUS - newly updated for 2013!
268 Transactions
All payment methods are secure and covered by SeekIC Buyer Protection PLUS.
The GS8161E18(T/D)/GS8161E32(D)/GS8161E36(T/D) is a 18,874,368-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.
Symbol |
Description |
Value |
Unit |
VDD |
Voltage on VDD Pins |
0.5 to 4.6 |
V |
VDDQ |
Voltage in VDDQ Pins |
0.5 to 4.6 |
V |
VI/O |
Voltage on I/O Pins |
0.5 to VDDQ +0.5 ( 4.6 V max.) |
V |
VIN |
Voltage on Other Input Pins |
0.5 to VDD +0.5 ( 4.6 V max.) |
V |
IIN |
Input Current on Any Pin |
+/20 |
mA |
IOUT |
Output Current on Any I/O Pin |
+/20 |
mA |
PD |
Package Power Dissipation |
1.5 |
W |
TSTG |
Storage Temperature |
55 to 125 |
oC |
TBIAS |
Temperature Under Bias |
55 to 125 |
oC |