GS8160Z18BT

Features:

• NBT (No Bus Turn Around) functionality allows zero wait
   read-write-read bus utilization; Fully pin-compatible with
   both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs
• 2.5 V or 3.3 V +10%/10% core power supply
• 2.5 V or 3.3 V I/O supply
• User-configurable Pipeline and Flow Through mode
• LBO pin for Linear or Interleave Burst mode
• Pin compatible with 2M, 4M, and 8M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 100-lead TQFP  package
• Pb-Free 100-lead TQFP package available


Pinout




Specifications

Symbol	Description	Value	Unit
VDD	Voltage on VDD Pins	0.5 to 4.6	V
VDDQ	Voltage in VDDQ Pins	0.5 to 4.6	V
VI/O	Voltage on I/O Pins	0.5 to VDDQ +0.5 ( 4.6 V max.)	V
VIN	Voltage on Other Input Pins	0.5 to VDD +0.5 ( 4.6 V max.)	V
IIN	Input Current on Any Pin	+/20	mA
IOUT	Output Current on Any I/O Pin	+/20	mA
PD	Package Power Dissipation	1.5	W
TSTG	Storage Temperature	55 to 125	o C
TBIAS	Temperature Under Bias	55 to 125	o C

Description

The GS8160Z18/36BT is an 18Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus  bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles.

Because GS8160Z18/36BT are synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control ( LBO ) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable (ZZ) and Output Enable. Output Enable GS8160Z18/36BT can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. GS8160Z18/36BT feature eliminates complex off-chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing.