Features: • FT pin for user-configurable flow through or pipeline operation • Dual Cycle Deselect (DCD) operation• 1.8 V +10%/10% core power supply• 1.8 V I/O supply•LBO pin for Linear or Interleaved Burst mode• Internal input resistors on mode pins allow floati...
GS8160EV18AT-350: Features: • FT pin for user-configurable flow through or pipeline operation • Dual Cycle Deselect (DCD) operation• 1.8 V +10%/10% core power supply• 1.8 V I/O supply•LB...
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The GS8160EV18/32/36AT is an 18,874,368-bit (16,777,216- bit for x32 version) high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.
Symbol | Description |
Value |
Unit |
VDD | Voltage on VDD Pins |
0.5 to 3.6 |
V |
VDDQ | Voltage on VDDQ Pins |
0.5 to 3.6 |
V |
VI/O | Voltage on I/O Pins |
0.5 to VDDQ +0.5 ( 3.6 V max.) |
V |
VIN | Voltage on Other Input Pins |
0.5 to VDD +0.5 ( 3.6 V max.) |
V |
IIN | Input Current on Any Pin |
+/20 |
mA |
IOUT | Output Current on Any I/O Pin |
+/20 |
mA |
PD | Package Power Dissipation |
1.5 |
W |
TSTG | Storage Temperature |
55 to 125 |
|
TBIAS | Temperature Under Bias |
55 to 125 |