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GS8150V36AB-357

Features: • Register-Register Late Write mode, Pipelined Read mode• 1.8 V +150/100 mV core power supply• 1.5 V or 1.8 V HSTL Interface• ZQ controlled programmable output drivers• Dual Cycle Deselect• Fully coherent read and write pipelines• Byte write oper...

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SeekIC No. : 004355786 Detail

GS8150V36AB-357: Features: • Register-Register Late Write mode, Pipelined Read mode• 1.8 V +150/100 mV core power supply• 1.5 V or 1.8 V HSTL Interface• ZQ controlled programmable output driv...

GS8150V36AB-357 Data Sheet

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Part Number:
GS8150V36AB-357
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Register-Register Late Write mode, Pipelined Read mode
• 1.8 V +150/100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• ZQ controlled programmable output drivers
• Dual Cycle Deselect
• Fully coherent read and write pipelines
• Byte write operation (9-bit bytes)
• Differential HSTL clock inputs, K and K
• Asynchronous output enable
• Sleep mode via ZZ
• IEEE 1149.1 JTAG-compliant Serial Boundary Scan
• JEDEC-standard 119-bump BGA package
• Pb-Free 119-bump BGA package available


Specifications

Symbol Description Value Unit
VDD Voltage on VDD Pins 0.5 to2.5 V
VDDQ Voltage in VDDQ Pins 0.5 to VDD V
VI/O Voltage on I/O Pins 0.5 to VDDQ+0.5 ( 2.5 V max.) V
VIN Voltage on Other Input Pins 0.5 to VDDQ+0.5 (2.5 V max.) V
IIN Input Current on Any Pin +/100 mAdc
IOUT Output Current on Any I/O Pin +/100 mAdc
TJ Maximum Junction Temperature 125
TSTG Storage Temperature 55 to 125

Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect reliability of this component.




Description

Because c are synchronous devices, address data inputs and read/write control inputs are captured on the rising edge of the input clock. Write cycles are internally selftimed and initiated by the rising edge of the clock input. GS8150V18/36A feature eliminates complex off-chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing.

GS8150V18/36A support pipelined reads utilizing a risingedge- triggered output register. They also utilize a Dual Cycle Deselect (DCD) output deselect protocol.
GS8150V18/36A are implemented with high performance HSTL technology and are packaged in a 119-bump BGA.




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