EPM7064BTI44-5N

The EPM7064BTI44-5N is one member of the EPM7064B family which is designed as the high-density, high-performance PLD. This device architecture is based on the linking of high-performance LABs and each LAB is fed by the following signals:(1)36 signals from the PIA that are used for general logic inputs; (2)global controls that are used for secondary register functions; (3)direct input paths from I/O pins to the registers that are used for fastsetup times.

Features of the EPM7064BTI44-5N are:(1)programmable power-saving mode for 50% or greater power reduction in each macrocell;(2)fast input setup times provided by a dedicated path from I/O pin to macrocell registers;(3)support for advanced I/O standards, including SSTL-2 and SSTL-3, and GTL+;(4)bus-hold option on I/O pins;(5)PCI compatible;(6)bus-friendly architecture including programmable slew-rate control;(7)6 to 10 pin- or logic-driven output enable signals.

The absolute maximum ratings of the EPM7064BTI44-5N can be summarized as:(1)supply voltage:-0.5 3.6 V;(2)DC input voltage:-2.0 to 4.6 V;(3)DC output current, per pin:-33 to 50 mA;(4)storage temperature:-65 to 150 °C;(5)ambient temperature:-65 to 135 °C;(6)junction temperature:-65 to 135. If you want to know more information such as the electrical characteristics about the EPM7064BTI44-5N, please download the datasheet in www.seekic.com or www.chinaicmart.com .