EPC16QC100

Features:

Enhanced configuration devices include EPC4, EPC8, and EPC16 devices
Single-chip configuration solution for Stratix® series, Cyclone™ series, APEX™ II, APEX 20K (including APEX 20K, APEX 20KC, and APEX 20KE), Mercury™, ACEX® 1K, and FLEX® 10K (FLEX 10KE and FLEX 10KA) devices
Contains 4-, 8-, and 16-Mbit flash memories for configuration data storage
    On-chip decompression feature almost doubles the effective configuration density
Standard flash die and a controller die combined into single stacked chip package
External flash interface supports parallel programming of flash and external processor access to unused portions of memory
    Flash memory block/sector protection capability via external flash interface
    Supported in EPC16 and EPC4 devices
Page mode support for remote and local reconfiguration with up to eight configurations for the entire system
    Compatible with Stratix series Remote System Configuration feature
Supports byte-wide configuration mode fast passive parallel (FPP); 8-bit data output per DCLK cycle
Supports true n-bit concurrent configuration (n = 1, 2, 4, and 8) of Altera FPGAs
Pin-selectable 2-ms or 100-ms power-on reset (POR) time
Configuration clock supports programmable input source and frequency synthesis
    Multiple configuration clock sources supported (internal oscillator and external clock input pin)
    External clock source with frequencies up to 133 MHz
    Internal oscillator defaults to 10 MHz; Programmable for higher frequencies of 33, 50, and 66 MHz
    Clock synthesis supported via user programmable divide counter
Available in the 100-pin plastic quad flat pack (PQFP) and the 88-pin Ultra FineLine BGA® packages
    Vertical migration between all devices supported in the 100-pin PQFP package
Supply voltage of 3.3 V (core and I/O)
Hardware compliant with IEEE Std. 1532 in-system programmability (ISP) specification
Supports ISP via Jam Standard Test and Programming Language (STAPL)
Supports Joint Test Action Group (JTAG) boundary scan
nINIT_CONF pin allows private JTAG instruction to initiate FPGA onfiguration
Internal pull-up resistor on nINIT_CONF always enabled
User programmable weak internal pull-up resistors on nCS and OE ins
Internal weak pull-up resistors on external flash interface address and control lines, bus hold on data lines
Standby mode with reduced power consumption


Description

The EPC16QC100 Altera enhanced configuration device is a single-device, high-speed, advanced configuration solution for very high-density FPGAs. The core of an enhanced configuration device is divided into two major blocks, a configuration controller and a flash memory. The flash memory is used to store configuration data for systems made up of one or more Altera FPGAs. Unused portions of the flash memory can be used to store processor code or data that can be accessed via the external flash interface after FPGA configuration is complete.

1 The EPC16QC100 external flash interface is currently supported in the EPC16 and EPC4 devices. For information on using this feature in the EPC8 device, contact Altera Applications. The enhanced configuration device has a 3.3-V core and I/O interface. The controller chip is a synchronous system that implements the various interfaces and features. Figure 21 shows a block diagram of the enhanced configuration device. The controller chip features three separate interfaces:

A configuration interface between the controller and the Altera FPGA(s)
A JTAG interface on the controller that enables in-system programmability (ISP) of the flash memory
An external flash interface that the controller shares with an external processor, or FPGA implementing a Nios® embedded processor (interface available after ISP and configuration)

The EPC16QC100 enhanced configuration device features multiple configuration schemes. In addition to supporting the traditional passive serial (PS) configuration scheme for a single device or a serial device chain, the enhanced configuration device features concurrent configuration and parallel configuration. With the concurrent configuration scheme, up to eight PS device chains can be configured simultaneously. In the FPP configuration scheme, 8-bits of data are clocked into the FPGA each cycle. These schemes offer significantly reduced configuration times over traditional schemes.

Furthermore, the EPC16QC100 enhanced configuration device features a dynamic configuration or page mode feature. This feature allows you to dynamically reconfigure all the FPGAs in your system with new images stored in the configuration memory. Up to eight different system configurations or pages can be stored in memory and selected using the PGM[2..0] pins. Your system can be dynamically reconfigured by selecting one of the eight pages and initiating a reconfiguration cycle. This page mode feature combined with the external flash interface allows remote and local updates of system configuration data. The enhanced configuration devices are compatible with the Stratix Remote System Configuration feature.


Parameters:

Technical/Catalog Information	EPC16QC100
Vendor	Altera
Category	Integrated Circuits (ICs)
Programmable Type	In System Programmable
Memory Size	16Mb
Package / Case	100-PQFP
Packaging	Tray
Voltage - Supply	3 V ~ 3.6 V
Operating Temperature	0°C ~ 70°C
Lead Free Status	Contains Lead
RoHS Status	RoHS Non-Compliant
Other Names	EPC16QC100 EPC16QC100 544 1226 ND 5441226ND 544-1226