EN25LF20

The EN25LF20 is a 2M-bit (256K-byte) Serial Flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction.The EN25LF20 is designed to allow either single Sector at a time or full chip erase operation. The EN25LF20 can be configured to protect part of the memory as the software protected mode. The device can sustain a minimum of 100K program/erase cycles on each sector.

Features of the EN25LF20 are:(1)lockable 256 byte OTP security sector; (2)minimum 100K endurance cycle; (3)industrial temperature range; (4)write protect all or portion of memory via software; (5)enable/disable protection with WP# pin.The SPI Serial Data Input (DI) pin provides a means for instructions, addresses and data to be serially written to (shifted into) the device. Data is latched on the rising edge of the Serial Clock (CLK) input pin.

The absolute maximum ratings of the EN25LF20 can be summarized as:(1)storage temperature:-65 to 125;(2)plastic packages:-65 to 125;(3)output short circuit current:200mA;(4)input and output voltage:-0.5 to 4.0 V;(5)Vcc:-0.5 to 4.0V.Stresses above the values so mentioned above may cause permanent damage to the device. These values are for a stress rating only and do not imply that the device should be operated at conditions up to or above these values. Exposure of the device to the maximum rating values for extended periods of time may adversely affect the device reliability.The EN25LF20 is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK), Chip Select (CS#), Serial Data Input (DI) and Serial Data Output (DO). Both SPI bus operation Modes 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3, as shown in Figure 3, concerns the normal state of the CLK signal when the SPI bus master is in standby and data is not being transferred to the Serial Flash. For Mode 0 the CLK signal is normally low. For Mode 3 the CLK signal is normally high. In either case data input on the DI pin is sampled on the rising edge of the CLK. Data output on the DO pin is clocked out on the falling edge of CLK.