EM78P451

The EM78P451 has the following features including Operating voltage range: 2.3V-5.5V;Serial Peripheral Interface (SPI) available;4K x 13 bits on chip ROM(EM78P451);11 special function registers.;140x 8 bits on chip general-purposed registers;5 bi-directional I/O ports (35 I/O pins);3 LED direct sinking pins with internal serial resistors;Built-in power-on reset;5 stacks for subroutine nesting;8-bit real time clock/counter (TCC) with overflow interrupt;Two machine clocks or four machine clocks per instruction cycle;Power down mode.

The EM78P451 is an 8-bit microprocessor designed and developed with low-power, high speed CMOS technology. Its operational kernel is implemented with RISC-like architecture and is available in the mask ROM version. The one time programmable (OTP) version is flexible, both in mass production or engineering test stages. OTP provide users with unlimited volume with favorable price opportunities. This device is equipped with the Serial Peripheral Interface (SPI) function and an easy-implemented RS-232.The EM78P451 is very suitable for wired communication. Only 58 easy-to-learn instructions are needed and user's program can be emulated with EMC In-Circuit Emulator (ICE).R0is not a physically implemented register. It is used as an indirect addressing pointer. Any instruction using RO as register actually accesses data pointed by the RAM Select Register (R4).The sleep mode (power down) is achieved by executing the SLEP instruction (named as SLEEP1 MODE). While entering sleep mode, the WDT (if enabled) is cleared but keeps on running. The controller is awakened by WDT timeout (if enabled), and it will cause the controller to reset. The T and P flags of R3 are used to determine the source of the reset (wake-up).

R3F is the interrupt status register, which records the interrupt request in flag bit. IOCF is the interrupt mask register. Global interrupt is enabled by ENI instruction and is disabled by DISI instruction. When one of the interrupts (if enabled) is generated, will cause the next instruction to be fetched from address 001 H. Once in the interrupt service routine the source of the interrupt can be determined by polling the flag bits in the R3F register. The interrupt flag bit must be cleared by software before leaving the interrupt service routine and enabling interrupts to avoid recursive interrupts.