EDE5104GBSA

Features:

1.8V power supply
Double-data-rate architecture: two data transfers per clock cycle
Bi-directional, differential data strobe (DQS and /DQS) is transmitted/received with data, to be used in capturing data at the receiver
DQS is edge aligned with data for READs: center-aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK transitions
Commands entered on each positive CK edge: data and data mask referenced to both edges of DQS 
Four internal banks for concurrent operation
Data mask (DM) for write data
Burst lengths: 4, 8
/CAS Latency (CL): 3, 4, 5
Auto precharge operation for each burst access
Auto refresh and self refresh modes
7.8s average periodic refresh interval
1.8V (SSTL_18 compatible) I/O
Posted CAS by programmable additive latency for better command and data bus efficiency
Off-Chip-Driver Impedance Adjustment and On-Die-Termination for better signal quality
Programmable RDQS, /RDQS output for making * 8  organization compatible to * 4 organization
/DQS, (/RDQS) can be disabled for single-ended Data Strobe operation.
BGA package is lead free solder (Sn-Ag-Cu) 
 


Pinout




Specifications

Parameter	Symbol	Rating	Unit	Note
Power supply voltage	VDD	-0.5 to +2.3	V	1
Power supply voltage for output	VDDQ	-0.5 to +2.3	V	1
Input voltage	VIN	-0.5 to +2.3	V	1
Output voltage	VOUT	-0.5 to +2.3	V	1
Operating temperature (ambient)	TA	0 to +70	°C	1
Storage temperature	Tstg	55 to +150	°C	1
Power dissipation	PD	1.0	W	1
Short circuit output current	IOUT	50	mA	1

Description

The EDE5104GB is a 512M bits DDR-II SDRAM organized as 33,554,432 words * 4 bits * 4 banks.   The EDE5108GB is a 512M bits DDR-II SDRAM organized as 16,777,216 words * 8 bits * 4 banks.   It packaged in 64-ball BGA^(R)  package.
 
The EDE5116GB is a 512M bits DDR-II SDRAM organized as 8,388,608 words * 16 bits * 4 banks.   It is packaged in 84-ball BGA package.