EDE5104AGSE-5C-E

Features: • Power supply: VDD, VDDQ =1.8V ±0.1V • Double-data-rate architecture: two data transfers per clock cycle • Bi-directional, differential data strobe (DQS and /DQS) is transmitted/received with data, to be used in capturing data at the receiver • DQS is edge aligne...

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EDE5104AGSE-5C-E Picture
SeekIC No. : 004333809 Detail

EDE5104AGSE-5C-E: Features: • Power supply: VDD, VDDQ =1.8V ±0.1V • Double-data-rate architecture: two data transfers per clock cycle • Bi-directional, differential data strobe (DQS and /DQS) is tra...

floor Price/Ceiling Price

Part Number:
EDE5104AGSE-5C-E
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/22

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Product Details

Description



Features:

• Power supply:  VDD, VDDQ = 1.8V ± 0.1V
• Double-data-rate architecture: two data transfers per clock cycle
• Bi-directional, differential data strobe (DQS and /DQS) is transmitted/received with data,
   to be used in capturing  data at the receiver
• DQS is edge aligned with data for READs: center-aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge: data and data mask referenced to both edges of DQS 
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• Burst lengths: 4, 8
• /CAS Latency (CL): 3, 4, 5
• Auto precharge operation for each burst access
• Auto refresh and self refresh modes
• Average refresh period  7.8µs at 0°C  TC  +85°C 
                                          3.9µs at +85°C < TC +95°C
• SSTL_18 compatible I/O
• Posted CAS by programmable additive latency for better command and data bus efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die-Termination for better signal quality
• Programmable RDQS, /RDQS output for making * 8 organization compatible to *4 organization
• /DQS, (/RDQS) can be disabled for single-ended Data Strobe operation.
• FBGA (µBGA) package with lead free solder (Sn-Ag-Cu)  RoHS compliant




Specifications

Parameter                                         Symbol                  Rating                Unit                   Notes

Power supply voltage                         VDD                     - 1.0 to +2.3            V                        1
Power supply voltage for output        VDDQ                  -  0.5 to +2.3            V                        1
Input voltage                                      VIN                     -  0.5 to +2.3            V                        1
Output voltage                                   VOUT                  -  0.5 to +2.3            V                         1
Storage temperature                          Tstg                    -  55 to +100                                  1,2
Power dissipation                                PD                         1.0                       W                       1
Short circuit output current                 IOUT                       50                       mA                      1



Description

The EDE5104AGSE is a 512M bits DDR2 SDRAM organized as 33,554,432 words × 4 bits × 4 banks.   The EDE5108AGSE is a 512M bits DDR2 SDRAM organized as 16,777,216 words × 8 bits × 4 banks.   They are packaged in 60-ball FBGA (µBGA® ) package.




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