EDD1232AABH

• Power supply:  VDDQ = 2.5V ± 0.2V 
                        :  VDD = 2.5V ± 0.2V
• Data rate: 333Mbps/266Mbps (max.)
• Double Data Rate architecture; two data transfers per clock cycle 
• Bi-directional, data strobe (DQS) is transmitted /received with data, to be used in capturing data at the receiver 
• Data inputs, outputs, and DM are synchronized with DQS
• 4 internal banks for concurrent operation
• DQS is edge aligned with data for READs; center aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Auto precharge option for each burst access
• SSTL_2 compatible I/O
• Programmable burst length (BL):  2, 4, 8
• Programmable /CAS latency (CL):  2, 2.5, 3
• Programmable output driver strength: half/weak
• Refresh cycles:  4096 refresh cycles/32ms  7.8µs maximum average periodic refresh interval
• 2 variations of refresh  Auto refresh   Self refresh
• FBGA package with lead free solder (Sn-Ag-Cu) RoHS compliant

The EDD1232AABH is a 128M bits DDR SDRAM organized as 1,048,576 words ×32 bits × 4 banks.  Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer EDD1232AABH is realized by the 2 bits prefetch-pipelined architecture.  Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. It is packaged in 144-ball FBGA package.