EBD21RD4ABNA

Features:

• 184-pin socket type dual in line memory module(DIMM)
        -PCB height: 30.48mm
        -Lead pitch: 1.27mm
• 2.5V power supply
• Data rate: 266Mbps/200Mbps (max.)
• 2.5 V (SSTL_2 compatible) I/O
• Double Data Rate architecture; two data transfers perclock cycle
• Bi-directional, data strobe (DQS) is transmitted/received with data, to be used in capturing data atthe receiver
• Data inputs and outputs are synchronized with DQS
• 4 internal banks for concurrent operation(Component)
• DQS is edge aligned with data for READs; centeraligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• LL aligns DQ and DQS transitions with CKtransitions
• Commands entered on each positive CK edge; datareferenced to both edges of DQS
• Auto precharge option for each burst access
• Programmable burst length: 2, 4, 8
• Programmable /CAS latency (CL): 2, 2.5
• Refresh cycles: (8192 refresh cycles /64ms)
        -7.8µs maximum average periodic refresh interval
• 2 variations of refresh
        -Auto refresh
        -Self refresh
• 1 piece of PLL clock driver, 1 piece of register driverand 1 piece of serial EEPROM (2k bits EEPROM) forPresence Detect (PD)


Specifications

Parameter	Symbol	Value	Unit	Note
Voltage on any pin relative to VSS	VT	1.0 to +3.6	V
Supply voltage relative to VSS	VDD, VDDQ	1.0 to +3.6	V
Short circuit output current	IOUT	50	mA
Power dissipation	PD	18	W
Operating ambient temperature	TA	0 to +70		1
Storage temperature	Tstg	-55 to +125

Description

The EBD21RD4ABNA is a 256M words × 72 bits, 2bank Double Data Rate (DDR) SDRAM Module,mounted 36 pieces of DDR SDRAM sealed in TCPpackage. Read and write operations are performed atthe cross points of the CK and the /CK. This high speed data transfer EBD21RD4ABNA is realized by the 2-bit prefetchpipelinedarchitecture. Data strobe (DQS) both forread and write are available for high speed and reliabledata bus design. By setting extended mode register,the on-chip Delay Locked Loop (DLL) can be setenable or disable. This module provides high densitymounting without utilizing surface mount technology.Decoupling capacitors are mounted beside each TCPon the module board.