DSM2190F4V

Features:

`Glueless Connection to DSP
Easily add memory, logic, and I/O to the External Port of ADSP-2191 DSP
`Dual Flash Memories
Two independent Flash memory arrays for storing DSP code and data. DSP may access the two arrays concurrently (read from one while erasing or writing the other)
256K x 8 Main Flash memory divided into 8 sectors (32KByte each)
Ample storage for booting DSP code/data upon reset and subsequent code swaps
Large capacity for data recording
32K x 8 Secondary Flash memory divided into sectors (8 KByte each). Multiple uses:
Small sector size ideal for small data sets, and calibration or configuration constants
Store custom start-up code in one or more sectors and configure DSP to run from external memory upon reset (no boot)
Concatenate Secondary Flash with Main Flash for total of 288 KBytes
Each Flash sector can be write protected.
Built-in programmable address decoding logic allows mapping individual Flash sectors to any address boundary
`Up to 16 Multifunction I/O Pins
Increase total DSP system I/O capability
I/O controlled by DSP software or PLD logic
`General purpose PLD
Over 3,000 Gates of PLD with 16 macro cells
Use for peripheral glue logic to keypads, control panel, displays, LCDs, and other devices
Eliminate PLDs and external logic devices
Create state machines, chip selects, simple shifters and counters, clock dividers, delays
Simple PSDsoft ExpressTM software...Free
`Operating Range
V<sub>CC</sub>: 3.3V±10%; Temperature: 40oC to +85oC
`In-System Programming (ISP) with JTAG
Program entire chip in 10-25 seconds with no involvement of the DSP
Links with ADSP-2191 JTAG debug port
Eliminate sockets for pre-programmed memory and logic devices
ISP allows efficient manufacturing and product testing supporting Just-In-Time inventory
Use low-cost FlashLINKTM cable with PC
`Content Security
Programmable Security Bit blocks access of device programmers and readers
`Zero-Power Technology
As low as 25mA standby current
`Packaging
52-pin PQFP or 52-pin PLCC
` Flash Memory Speed, Endurance, Retention
150 ns, 100K cycles, 15 year retention


Pinout




Specifications

Symbol	Parameter	Min.	Max.	Unit
TSTG	Storage Temperature	65	125	°C
TLEAD	Lead Temperature during Soldering (20 seconds max.)1		235	°C
VIO	Input and Output Voltage (Q = VOH or Hi-Z)	0.6	7.0	V
VCC	Supply Voltage	0.6	7.0	V
VPP	Device Programmer Supply Voltage	0.6	14.0	V
VESD	Electrostatic Discharge Voltage (Human Body model) 2	2000	2000	V

Description

The DSM2190F4 is a system memory device for use with the Analog Devices ADSP-2191 DSP. DSM means Digital signal processor System Memory. A DSM device brings In-System Programmable (ISP) Flash memory, parameter storage, programmable logic, and additional I/O to DSP systems. The result is a simple and flexible two-chip solution for DSP designs. DSM devices DSM2190F4V provide the flexibility of Flash memory and smart JTAG programming techniques for both manufacturing and the field. On-chip integrated memory decode logic makes it easy to map dual banks of Flash memory to the ADSP-2191 in a variety of ways for bootloading, code execution, data recording, code swapping, and parameter storage.

JTAG ISP reduces development time, simplifies manufacturing flow, and lowers the cost of field upgrades. The DSM2190F4V JTAG ISP interface eliminates the need for sockets and pre-programmed memory and logic devices. For manufacturing, end products may be assembled with a blank DSM device soldered to the circuit board and programmed at the end of the manufacturing line in 10 to 25 seconds with no involvement of the DSP. This allows efficient means to test product and manage inventory by rapidly programming test code, then application code as determined by inventory requirements (Just-In Time inventory). Additionally, JTAG ISP reduces development time by turning fast iterations of DSP code in the lab. Code updates in the field require no disassembly of product. The FlashLINKTM JTAG programming cable costs $59 USD and plugs into any PC or notebook parallel port.

In addition to ISP Flash memory, DSM devices DSM2190F4V add programmable logic (PLD) and up to 16 configurable I/O pins to the DSP system. The state of each I/O pin can be driven by DSP software or PLD logic. PLD and I/O configuration are programmable by JTAG ISP, just like the Flash memory. The PLD consists of more than 3000 gates and has 16 macro cell registers. Common uses for the PLD include chip selects for external devices, state-machines, simple shifters and counters, keypad and control panel interfaces, clock dividers, handshake delay, multiplexers, etc. This eliminates the need for small external PLDs and logic devices. Configuration of PLD, I/O, and Flash memory mapping are easily entered in a pointand- click environment using the software development tool, PSDsoft ExpressTM. This software is available at no charge from www.st.com/psm.