DSM2180F3

Features:

`Glueless Connection to DSP
Easily add memory, logic, and I/O to DSP
`128K Byte Flash Memory
For Bootloading and/or Data Overlay Memory
Programmable Decoding and Paging Logic allows accessing Flash memory as Byte DMA BDMA) and as External Data Overlay memory
Rapidly access Flash memory with BDMA for booting and loading internal DSP Overlay memory. Alternatively access the same Flash memory as External Data Overlay memory to efficiently write Flash memory with code updates and data, a byte at a time with no DMA setup overhead
Individual 16K Byte Flash memory sectors match size of DSP External Data Overlay window for efficient data management. Integrated page logic provides easy DSP access to all 128K Bytes.
DSM connects to lower byte of 16-bit DSP data bus. Byte-wide accesses to 8-bit BDMA space. Half-word accesses to 16-bit Data Memory Overlay and 16-bit I/O Mem space.
`5V Devices (±10%)
`Up to 16 Multifunction I/O Pins
Increase total DSP system I/O capability
I/O controlled by DSP software or PLD logic
8mA I/O pin drive at 5 Vcc
`General purpose PLD
Over 3,000 Gates of PLD with 16 macro cells
Use for peripheral glue logic to keypads, control panel, displays, LCD, UART devices, etc.
Eliminate PLDs and external logic devices
Create state machines, chip selects, simple shifters and counters, clock dividers, delays
Simple PSDsoft ExpressTM software ...Free
`In-System Programming (ISP) with JTAG
Program entire chip in 10-20 seconds with no involvement of the DSP
Eliminate sockets for pre-programmed memory and logic devices
Efficient manufacturing allows easy product testing and Just-In-Time inventory
Use low-cost FlashLINK^TM cable with PC
`Content Security
Programmable Security Bit blocks access of device programmers and readers
`Zero-Power Technology
75 mA standby at VCC=5V
`Small Packaging
52-pin PQFP or 52-pin PLCC
`Memory Speed
90 ns


Pinout




Specifications

Symbol	Parameter	Min.	Max.	Unit
TSTG	Storage Temperature	65	125	°C
TLEAD	Lead Temperature during Soldering (20 seconds max.)1		235	°C
VIO	Input and Output Voltage (Q = VOH or Hi-Z)	0.6	7.0	V
VCC	Supply Voltage	0.6	7.0	V
VPP	Device Programmer Supply Voltage	0.6	14.0	V
VESD	Electrostatic Discharge Voltage (Human Body model) 2	2000	2000	V

Description

These are system memory devices DSM2180F3 for use with Digital Signal Processors from the popular Analog Devices ADSP-218X family. DSM means Digital signal processor System Memory. A DSM device brings in-system programmable Flash memory, programmable logic, and additional I/O to DSP systems. The result is a simple and flexible twochip solution for DSP designs. DSM devices provide the flexibility of Flash memory and smart JTAG programming techniques for both manufacturing and the field. On-chip integrated memory decode logic and memory paging logic make it easy to add large amounts of external Flash memory to the ADSP-218X family for bootloading upon power-up and/or overlay memory. The DSP accesses this Flash memory using either its Byte DMA (BDMA) interface or as external data overlay memory (no DMA setup overhead).

DSM2180F3 JTAG In-System Programming (ISP) reduces development time, simplifies manufacturing flow, and lowers the cost of field upgrades. The JTAG ISP interface eliminates the need for sockets and pre-programmed memory and logic devices. For manufacturing, end products may be assembled with a blank DSM device soldered to the circuit board and programmed at the end of the manufacturing line in 10 to 20 seconds with no involvement of the DSP. This allows efficient means to test product and manage inventory by rapidly programming test code, then application code as determined by inventory requirements (Just-In Time inventory). Additionally, JTAG ISP reduces development time by turning fast iterations of DSP code in the lab. Code updates in the field require no disassembly of product. The FlashLINKTM JTAG programming cable costs $59 USD and plugs into any PC or note-book parallel port.

In addition to ISP Flash memory, DSM devices DSM2180F3 add programmable logic (PLD) and up to 16 configurable I/O pins to the DSP system. The state of each I/O pin can be driven by DSP software or PLD logic. PLD and I/O configuration are programmable by JTAG ISP, just like the Flash memory.

The DSM2180F3 PLD consists of more than 3000 gates and has 16 macro cell registers. Common uses for the PLD include chip selects for external devices (i.e. UART), state-machines, simple shifters and counters, keypad and control panel interfaces, clock dividers, handshake delay, muxes, etc. This eliminates the need for small external PLDs and logic devices.

Configuration of PLD, I/O, and Flash memory mapping are easily entered in a pointand- click environment using the software development tool, PSDsoft ExpressTM. This software is available at no charge from www.psdst.com.