Product Type
:
Normalling
:
Height / Number of Racks
:
Depth
:
Termination Style
:
Number of Positions / Contacts
:
Features: • Very low cost, high-performance logic solution for high-volume, consumer-oriented applications
• Proven advanced 90-nanometer process technology
• Multi-voltage, multi-standard SelectIO™ interface pins
- Up to 376 I/O pins or 156 differential signal pairs
- LVCMOS, LVTTL, HSTL, and SSTL single-ended signal standards
- 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling
- 622+ Mb/s data transfer rate per I/O
- True LVDS, RSDS, mini-LVDS, differential HSTL/SSTL differential I/O
- Enhanced Double Data Rate (DDR) support
- DDR SDRAM support up to 333 Mb/s
• Abundant, flexible logic resources
- Densities up to 33,192 logic cells, including optional shift register or distributed RAM support
- Efficient wide multiplexers, wide logic
- Fast look-ahead carry logic
- Enhanced 18 x 18 multipliers with optional pipeline
- IEEE 1149.1/1532 JTAG programming/debug port
• Hierarchical SelectRAM™ memory architecture
- Up to 648 Kbits of fast block RAM
- Up to 231 Kbits of efficient distributed RAM
• Up to eight Digital Clock Managers (DCMs)
- Clock skew elimination (delay locked loop)
- Frequency synthesis, multiplication, division
- High-resolution phase shifting
- Wide frequency range (5 MHz to over 300 MHz)
• Eight global clocks plus eight additional clocks per each half of device, plus abundant low-skew routing
• Configuration interface to industry-standard PROMs
- Low-cost, space-saving SPI serial Flash PROM
- x8 or x8/x16 parallel NOR Flash PROM
- Low-cost Xilinx Platform Flash with JTAG
• Complete Xilinx ISE™ and WebPACK™ development system support
• MicroBlaze™ and PicoBlaze™ embedded processor cores
• Fully compliant 32-/64-bit 33 MHz PCI support (66 MHz in some devices)
• Low-cost QFP and BGA packaging options
- Common footprints support easy density migration
- Pb-free packaging optionsPinout
Specifications
| Symbol |
Description |
Conditions |
Min |
Max |
Units |
| VCCINT |
Internal supply voltage |
|
0.5 |
1.32 |
V |
| VCCAUX |
Auxiliary supply voltage |
|
0.5 |
3.00 |
V |
| VCCO |
Output driver supply voltage |
|
0.5 |
3.75 |
V |
| VREF |
Input reference voltage |
|
0.5 |
VCCO+0.5(1) |
V |
VIN
(1,2,3) |
Voltage applied to all User I/O pins and
Dual-Purpose pins |
Driver in a
high-impedance
state |
Commercial |
0.95 |
4.4 |
V |
| Industrial |
0.85 |
4.3 |
V |
| Voltage applied to all Dedicated pins |
All temp. ranges |
0.5 |
VCCAUX+0.5(3) |
V |
| IIK |
Input clamp current per I/O pin |
0.5 V < VIN < (VCCO + 0.5 V) |
|
±100 |
mAV |
| VESD |
Electrostatic Discharge Voltage |
Human body model |
|
±2000 |
V |
| Charged device model |
|
±500 |
V |
| Machine model |
|
±200 |
V |
| TJ |
Junction temperature |
|
|
125 |
|
| TSTG |
Storage temperature |
|
65 |
150 |
|
Notes:
1. Each of the User I/O and Dual-Purpose pins is associated with one of the four banks' VCCO rails. Keeping VIN within 500 mV of the associated VCCO rails or ground rail ensures that the internal diode junctions do not turn on. Table 76 specifies the VCCO range used to evaluate the maximum VIN voltage.
2. Input voltages outside the -0.5V to VCCO + 0.5V voltage range are permissible provided that the IIK input diode clamp diode rating is met and no more than 100 pins exceed the range simultaneously.
3. All Dedicated pins (PROG_B, DONE, TCK, TDI, TDO, and TMS) draw power from the VCCAUX rail (2.5V). Meeting the VIN max limit ensures that the internal diode junctions that exist between each of these pins and the VCCAUX rail do not turn on. Table 76 specifies the VCCAUX range used to evaluate the maximum VIN voltage. As long as the VIN max specification is met, oxide stress is not possible.
4. For soldering guidelines, see UG112: Device Packaging and Thermal Characteristics and XAPP427: Implementation and Solder Reflow Guidelines for Pb-Free Packages.
DescriptionThe DS312 Spartan™-3E family of Field-Programmable Gate Arrays (FPGAs) is specifically designed to meet the needs of high volume, cost-sensitive consumer electronic applications.
The DS312 five-member family offers densities ranging from 100,000 to 1.6 million system gates, as shown in Table 1.
The DS312 Spartan-3E family builds on the success of the earlier Spartan-3 family by increasing the amount of logic per I/O,significantly reducing the cost per logic cell. New features improve system performance and reduce the cost of configuration.
These Spartan-3E enhancements DS312, combined with advanced 90 nm process technology, deliver more functionality and bandwidth per dollar than was previously possible, setting new standards in the programmable logic industry.
Because of their exceptionally low cost, Spartan-3E FPGAs DS312 are ideally suited to a wide range of consumer electronics applications, including broadband access, home networking, display/projection, and digital television equipment.
The DS312 Spartan-3E family is a superior alternative to mask programmed ASICs. FPGAs avoid the high initial cost, the lengthy development cycles, and the inherent inflexibility of conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary, an impossibility with ASICs.
DS312 Data Sheet
