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DS3100

Features: ·Synchronization Subsystem for Stratum 3E, 3,4E and 4, SMC and SEC - Meets Requirements of GR-1244 Stratum 3/3E,GR-253, G.812 Types I, III and IV, and G.813 - Stratum 3E Holdover Accuracy with Suitable External Oscillator - Programmable Bandwidth, 0.5mHz to 70Hz - Hitless Reference Switc...

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SeekIC No. : 004328976 Detail

DS3100: Features: ·Synchronization Subsystem for Stratum 3E, 3,4E and 4, SMC and SEC - Meets Requirements of GR-1244 Stratum 3/3E,GR-253, G.812 Types I, III and IV, and G.813 - Stratum 3E Holdover Accuracy ...

DS3100 Data Sheet

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Part Number:
DS3100
Supply Ability:
5000

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  • 1~5000
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  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/23

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Product Details

Description



Features:

·Synchronization Subsystem for Stratum 3E, 3,4E and 4, SMC and SEC
   - Meets Requirements of GR-1244 Stratum 3/3E,GR-253, G.812 Types I, III and IV, and G.813
   - Stratum 3E Holdover Accuracy with Suitable External Oscillator
   - Programmable Bandwidth, 0.5mHz to 70Hz
   - Hitless Reference Switching on Loss of Input
   - Phase Build   -Out and Transient Absorption
   - Locks to and Generates 125MHz for Gigabit Synchronous Ethernet per ITU-T G.8261
·14 Input Clocks
   - 10 CMOS/TTL Inputs Accept 2kHz, 4kHz, and Any Multiple of 8kHz Up to 125MHz
   - Two LVDS/LVPECL/CMOS/TTL Inputs Accept Nx8kHz Up to 125MHz Plus 155.52MHz
   - Two 64kHz Composite Clock Receivers
   - Continuous Input Clock Quality Monitoring
   - Separate 2/4/8kHz Frame Sync Input
·11 Output Clocks
   - Five CMOS/TTL Outputs Drive Any Internally Produced Clock Up to 77.76MHz
   - Two LVDS Outputs Each Drive Any Internally Produced Clock Up to 311.04MHz
   - One 64kHz Composite Clock Transmitter
   - One 1.544MHz/2.048MHz Output Clock
   - Two Sync Pulses: 8kHz and 2kHz
   - Output Clock Rates Include 2kHz, 8kHz, NxDS1,NxDS2, DS3, NxE1, E3, 6.48MHz, 19.44MHz,38.88MHz, 51.84MHz, 62.5MHz, 77.76MHz,125MHz, 155.52MHz, 311.04MHz
·Two Multiprotocol BITS/SSU Transceivers
   - Receive and Transmit DS1, E1, 2048kHz, and 6312kHz Timing Signals
   - Insert and Extract SSM Messages (DS1, E1)
   - Automatically Invalidate Clocks on LOS, OOF, AIS, and Other Defects
·Internal Compensation for Master Clock Oscillator Frequency Accuracy
·Processor Interface: 8   -Bit Parallel or SPI Serial
·1.8V Operation with 3.3V I/O (5V Tolerant)


Application

· SONET/SDH ADMs, MSPPs, and MSSPs
· Digital Cross-Connects
· DSLAMs
· Service Provider Routers


Specifications

Voltage Range on Any Pin with Respect to VSS (except VDD).......-0.3V to +5.5V
Supply Voltage Range (VDD) with Respect to VSS..............-0.3V to +1.98V
Supply Voltage Range (VDDIO) with Respect to VSS.............-0.3V to +3.63V
Ambient Operating Temperature Range............-40°C to +85°C (Note 1)
Junction Operating Temperature Range................-40°C to +125°C
Storage Temperature Range.....................-55°C to +125°C
Soldering Temperature..............See IPC/JEDEC J-STD-020 Specification

Note 1: Specifications to -40°C are guaranteed by design and not production tested.

Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device. Ambient operating temperature range when device is mounted on a four-layer JEDEC test board with no airflow.


Description

When paired with an external TCXO or OCXO, the DS3100 is a complete central timing and synchronization solution for SONET/SDH network elements. With two multiprotocol BITS/SSU receivers and 14 input clocks, the device directly accepts both external timing and line timing from a large number of line cards. All input clocks are continuously monitored for frequency accuracy and activity. Any two of the input clocks can be selected as the references for the two core DPLLs. The T0 DPLL complies with the Stratum 3 and 3E requirements of GR1244, GR-253, and the requirements of G.812 Type III and G.813. From the output of the core DPLLs, a wide variety of output clock frequencies and frame pulses can be produced simultaneously on the 11 output clock pins. Two DS3100 devices can be configured in a master/slave arrangement for timing card equipment protection.

The DS3100 registers and I/O pins are backward compatible with Semtech's ACS8520 and ACS8530 timing card ICs.




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